Alternatives and similar repositories for fixSegfaultVCS

Users that are interested in fixSegfaultVCS are comparing it to the libraries listed below

• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆117Updated 4 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆110Updated 2 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆84Updated 5 months ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year
• zion-group / VerilogCodingStyle
  ☆65Updated 5 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆77Updated 5 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆44Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆108Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆93Updated 4 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆73Updated 6 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆20Updated 2 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• hyf6661669 / verilog_library
  HYF's high quality verilog codes
  ☆16Updated last year
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆126Updated 3 years ago
• limerainne / Dockerize-EDA
  [WIP] Dockerize Synopsys/Cadence EDA tools
  ☆95Updated 6 years ago
• accellera / uvm
  ☆60Updated 9 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆84Updated 7 years ago
• ForrestBlue / cortexm0ds
  ☆74Updated 10 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆101Updated 5 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆203Updated 4 months ago
• hjking / uvm_gen
  UVM Generator
  ☆50Updated last year
• bytedance / ic_flow_platform
  IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …
  ☆191Updated 3 weeks ago
• BinaryHackerLab / SynopsysMonoSlayer
  Synopsys License patcher
  ☆37Updated last year
• emwzq / example_uvm
  UVM实战随书源码
  ☆57Updated 6 years ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆26Updated last year
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• wudayemen / gen_apb_file
  ☆75Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆52Updated 10 years ago