baichen318 / FreePDK45Links
This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology
☆30Updated 4 years ago
Alternatives and similar repositories for FreePDK45
Users that are interested in FreePDK45 are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆187Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆37Updated 5 years ago
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- ☆194Updated 6 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆51Updated last year
- ☆44Updated last year
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- ☆174Updated 4 years ago
- ☆88Updated this week
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆76Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆85Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure …☆74Updated 4 years ago
- ☆43Updated 3 years ago
- SRAM☆22Updated 5 years ago
- ☆26Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆49Updated 4 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆21Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- Open source process design kit for 28nm open process☆61Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆95Updated 3 months ago
- sram/rram/mram.. compiler☆42Updated 2 years ago
- ☆47Updated last year
- A 10bit SAR ADC in Sky130☆25Updated 2 years ago
- A free standard cell library for SDDS-NCL circuits☆28Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- A Standalone Structural Verilog Parser☆97Updated 3 years ago
- Static Timing Analysis Full Course☆60Updated 2 years ago
- ☆78Updated 10 years ago