swetland / os-workshopLinks
Some materials and sample source for RV32 OS projects.
☆21Updated 3 years ago
Alternatives and similar repositories for os-workshop
Users that are interested in os-workshop are comparing it to the libraries listed below
Sorting:
- Experiments with Yosys cxxrtl backend☆50Updated last year
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- Small footprint and configurable HyperBus core☆14Updated 3 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Updated 6 years ago
- PLEASE MOVE TO PAWSv2☆16Updated 4 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- ☆44Updated 11 months ago
- PicoRV☆43Updated 5 years ago
- LiteX development baseboards arround the SQRL Acorn.☆73Updated 10 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 8 months ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆32Updated last week
- CologneChip GateMate FPGA Module: GMM-7550☆28Updated 3 weeks ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆68Updated 9 months ago
- Bit streams forthe Ulx3s ECP5 device☆18Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Updated 2 months ago
- My pergola FPGA projects☆30Updated 4 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 4 years ago
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Updated last month
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month
- 妖刀夢渡☆63Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- Tiny tips for Colorlight i5 FPGA board☆65Updated 4 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- Exploring gate level simulation☆58Updated 9 months ago
- ☆22Updated 3 years ago