waviousllc / wav-lpddr-swLinks
Wavious DDR (WDDR) Physical interface (PHY) Software
☆22Updated 3 years ago
Alternatives and similar repositories for wav-lpddr-sw
Users that are interested in wav-lpddr-sw are comparing it to the libraries listed below
Sorting:
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Open Source PHY v2☆31Updated last year
- APB UVC ported to Verilator☆11Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- ☆38Updated 3 years ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- ☆33Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- Extended and external tests for Verilator testing☆17Updated last week
- Test dashboard for verification features in Verilator☆28Updated last week
- submission repository for efabless mpw6 shuttle☆31Updated last year
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆53Updated 5 months ago
- ☆44Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- ☆40Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆40Updated 2 years ago
- Advanced Debug Interface☆14Updated 11 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated last month
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- A configurable SRAM generator☆56Updated 4 months ago