waviousllc / wav-lpddr-sw
Wavious DDR (WDDR) Physical interface (PHY) Software
☆19Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for wav-lpddr-sw
- SCARV: a side-channel hardened RISC-V platform☆24Updated last year
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- ☆36Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- ☆33Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- YosysHQ SVA AXI Properties☆32Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆21Updated 2 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- ☆21Updated 7 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- LibreSilicon's Standard Cell Library Generator☆17Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- RISC-V soft-core PEs for TaPaSCo☆15Updated 5 months ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- A padring generator for ASICs☆22Updated last year
- Library of open source Process Design Kits (PDKs)☆28Updated last week
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- ☆18Updated 4 years ago