Alternatives and similar repositories for lpddr4-testbed:

Users that are interested in lpddr4-testbed are comparing it to the libraries listed below

• antmicro / rdimm-ddr4-tester
  Experimental platform built around Xilinx Kintex-7 FPGA for development and customization of RAM controllers supporting RDIMM DDR4 RAM mo…
  ☆13Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆55Updated last month
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆20Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆25Updated 3 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆19Updated 4 months ago
• enjoy-digital / pcie_analyzer
  PCIe analyzer experiments
  ☆49Updated 4 years ago
• XUANTIE-RV / buildroot
  Buildroot customized for Xuantie™ RISC-V CPU
  ☆42Updated 3 years ago
• riscvarchive / riscv-zfinx
  ☆12Updated last year
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆70Updated this week
• DUNE / pl-nvme
  ☆27Updated 4 years ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆26Updated 4 months ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆34Updated last year
• antmicro / lpddr4-test-board
  Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM
  ☆36Updated last year
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆21Updated 5 years ago
• sergachev / litex-template
  Template project for LiteX-based SoCs
  ☆19Updated 7 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 3 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆41Updated last month
• regymm / SqueakyBoard
  My self-designed ZYNQ-7010 4-layer developement board.
  ☆29Updated 3 years ago
• xyzxinyizhang / FPGA-SFP-communication-with-Aurora
  ☆17Updated 6 years ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• Cosmos-OpenSSD / Cosmos-OpenSSD
  ☆43Updated 7 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• OpenCAPI / OpenCAPI3.0_Client_RefDesign
  An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
  ☆13Updated 2 years ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• riscveval / Rocket-Chip
  ☆21Updated 7 years ago