Alternatives and similar repositories for coeus-sim

Users that are interested in coeus-sim are comparing it to the libraries listed below

• sylab / multi-clock
  Sources for the Multi-Clock system as described in the paper: MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems, HPCA 2022.
  ☆19Updated 3 years ago
• project-kona / asplos21-ae
  ☆31Updated 4 years ago
• ysarch-lab / nimble_page_management_userspace
  ☆13Updated 6 years ago
• casys-kaist / AMP
  Adaptive Page Migration Policy with Huge Pages in Tiered Memory Systems
  ☆16Updated 4 years ago
• csl-iisc / Trident-MICRO21-artifact
  ☆11Updated 2 years ago
• BLepers / JohnnyCache
  Johnny Cache: the End of DRAM Cache Conflicts (in Tiered Main Memory Systems)
  ☆20Updated 2 years ago
• Sys-KU / AutoTiering
  [USENIX ATC 2021] Exploring the Design Space of Page Management for Multi-Tiered Memory Systems
  ☆48Updated 3 years ago
• GTkernel / cori-sim
  Simulation infrastructure and validation of Cori
  ☆13Updated 3 years ago
• clusterfarmem / cfm
  Cluster Far Mem, framework to execute single job and multi job experiments using fastswap
  ☆21Updated last year
• host-architecture / colloid
  Tiered Memory Management: Access Latency is the Key!
  ☆61Updated 9 months ago
• WukLab / Clio
  Clio, ASPLOS'22.
  ☆78Updated 3 years ago
• madsys-dev / sosp-paper19-ae
  The Artifact Evaluation Version of SOSP Paper #19
  ☆52Updated last year
• sslab-gatech / latr
  Latr: Lazy Translation Coherence - ASPLOS'18
  ☆15Updated 4 years ago
• FAST-UIUC / iat-pqos
  Enhanced PQOS (Intel RDT Software) with DDIO-related Functionalities
  ☆16Updated 3 years ago
• ece-fast-lab / cxl_type3_tests
  This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Device…
  ☆51Updated last year
• lingfenghsiang / Nomad
  OSDI'24 Nomad implementation
  ☆55Updated 5 months ago
• spypaul / MQSim_CXL
  ☆75Updated 2 years ago
• TheNetAdmin / VANS
  VANS: A validated NVRAM simulator
  ☆26Updated 2 years ago
• TianheMICALab / SimCXL
  CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation
  ☆116Updated 2 months ago
• ysarch-lab / nimble_page_management_asplos_2019
  Kernel repo of "Nimble Page Management for Tiered Memory Systems" in ASPLOS 2019
  ☆46Updated 3 years ago
• ece-fast-lab / ASPLOS-2025-M5
  This is the respository that holds the artifacts of ASPLOS'25 -- M5: Mastering Page Migration and Memory Management for CXL-based Tiered …
  ☆15Updated 9 months ago
• clusterfarmem / clustersim
  Cluster simulator with far memory
  ☆12Updated 5 years ago
• cosmoss-jigu / memtis
  Tiered memory management
  ☆86Updated 4 months ago
• cloudarxiv / emucxl
  ☆17Updated last year
• Compute-Express-Link / CXLPapers
  ☆112Updated 2 years ago
• bsc-mem / Mess-benchmark
  A Multiplatform benchmark designed to provide holistic, detailed and close-to-hardware view of memory system performance with family of b…
  ☆42Updated 2 months ago
• zainryan / INSIDER-System
  An FPGA-based full-stack in-storage computing system.
  ☆38Updated 5 years ago
• zxhero / gem5-CXL
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆38Updated last year
• multifacet / cbmm-artifact
  Artifact package for CBMM paper (ATC'22)
  ☆11Updated 3 years ago
• MoatLab / Pond
  Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (ASPLOS'23)
  ☆216Updated last year