Alternatives and similar repositories for Chiplet-Gem5-SharedMemory

Users that are interested in Chiplet-Gem5-SharedMemory are comparing it to the libraries listed below

• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆86Updated 6 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆75Updated last year
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆48Updated 7 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year
• Yinxiao-Feng / chiplet-network-sim
  ☆55Updated 8 months ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆47Updated 3 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆71Updated last month
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆56Updated 4 years ago
• UIUC-ChenLab / Nimblock
  ☆13Updated 2 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 4 years ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆108Updated 9 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆82Updated 10 months ago
• sangjae4309 / gem5-ramulator2
  This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…
  ☆13Updated 8 months ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 4 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆62Updated 10 months ago
• UniNDP-hpca25-ae / UniNDP
  Artifact material for [HPCA 2025] #2108 "UniNDP: A Unified Compilation and Simulation Tool for Near DRAM Processing Architectures"
  ☆53Updated 5 months ago
• PolyArch / gem-forge-framework
  ☆26Updated 2 years ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆91Updated 2 years ago
• scalesim-project / scale-sim-v3
  ☆57Updated 2 months ago
• breagen / MachSuite
  Benchmarks for Accelerator Design and Customized Architectures
  ☆136Updated 5 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 3 years ago
• joaomiguelvieira / gem5-accel
  ☆16Updated 2 years ago
• hngenc / stellar
  ☆33Updated last year
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 4 years ago