FCAS-LAB / chiplet_simulatorsLinks
A list of our chiplet simulaters
☆35Updated 2 months ago
Alternatives and similar repositories for chiplet_simulators
Users that are interested in chiplet_simulators are comparing it to the libraries listed below
Sorting:
- An integrated CGRA design framework☆90Updated 5 months ago
- ☆40Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 4 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆23Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆28Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- gem5 repository to study chiplet-based systems☆79Updated 6 years ago
- An Open-Source Tool for CGRA Accelerators☆23Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆136Updated 2 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated 11 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆58Updated last month
- ☆57Updated 5 months ago
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆87Updated 4 months ago
- ☆31Updated last year
- ☆35Updated 8 months ago
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- ☆31Updated 9 months ago
- ☆13Updated 2 years ago
- A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0☆31Updated last month
- Dataset for ML-guided Accelerator Design☆37Updated 9 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- ☆11Updated last year
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆69Updated 5 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year