An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
☆109Oct 21, 2026Updated this week
Alternatives and similar repositories for chia
Users that are interested in chia are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Mar 11, 2026Updated 7 months ago
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆27Jun 14, 2026Updated 4 months ago
- A GPU built from scratch which can render graphics and train ML models☆15Jul 4, 2026Updated 3 months ago
- Virtualized Accelerator Orchestration for Multi-Tenant Workloads☆23Nov 17, 2024Updated last year
- Digital logic benchmark suite☆93Sep 28, 2026Updated 3 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆20Oct 2, 2026Updated 3 weeks ago
- Autocomp: Optimize any AI kernel, anywhere.☆151Jul 11, 2026Updated 3 months ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆19May 22, 2025Updated last year
- ☆15Jul 28, 2026Updated 2 months ago
- wzv — record now, get waveforms later☆25Aug 29, 2026Updated last month
- Evidence profiles for AI-generated RTL that expose what functional benchmarks miss. Seeking collaborators, design partners, and validatio…☆21Sep 28, 2026Updated 3 weeks ago
- Open-Hardware implementation of the icsprout55-pdk☆18Oct 10, 2026Updated last week
- ☆31Aug 25, 2026Updated last month
- ☆21Sep 14, 2026Updated last month
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- ☆14Mar 20, 2025Updated last year
- A PCIe RTL implementation☆26Aug 16, 2026Updated 2 months ago
- Open-source compiler that hardwires ternary BitNet weights into mask-programmed compute-in-ROM silicon on open PDKs☆47Sep 18, 2026Updated last month
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆21Oct 10, 2026Updated last week
- a Chicken Scheme port of the QuickCheck unit test framework☆13May 9, 2020Updated 6 years ago
- The Scala parser to parse riscv/riscv-opcodes generate☆26Jan 21, 2026Updated 9 months ago
- A library of open PDK packages☆138Oct 13, 2026Updated last week
- Nix template for the chisel-based industrial designing flows.☆58Jul 21, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ARCH hardware description language and compiler☆78Updated this week
- ☆15Sep 30, 2026Updated 3 weeks ago
- TransPimLib is a library for transcendental (and other hard-to-calculate) functions in general-purpose PIM systems, TransPimLib provides …☆15Apr 21, 2023Updated 3 years ago
- ☆27Aug 2, 2021Updated 5 years ago
- Tiny Tapeout Explorer is an interactive web-based visualization tool for exploring integrated circuit designs from the Tiny Tapeout commu…☆24Jul 30, 2026Updated 2 months ago
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆48Updated this week
- TAIDL: Tensor Accelerator ISA Definition Language☆25Updated this week
- Open source RTL simulation acceleration on commodity hardware☆37Apr 13, 2023Updated 3 years ago
- An open-source UCIe implementation☆137Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- M3D routing challenge: a reproducible EDA routing benchmark for a simplified monolithic-3D stack (generator, checker, scorer, baseline, v…☆51Updated this week
- Xiangshan deterministic workloads generator☆29Oct 14, 2026Updated last week
- The 'missing header' for Chisel☆24Feb 5, 2026Updated 8 months ago
- ☆14Aug 5, 2023Updated 3 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆34Sep 29, 2026Updated 3 weeks ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,429Updated this week
- This project proposes a distributed communication protocol called MPIQ (Classical-Quantum Message Passing Interface) for the "classical +…☆16Apr 2, 2026Updated 6 months ago