Alternatives and similar repositories for learnsystemc:

Users that are interested in learnsystemc are comparing it to the libraries listed below

• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆103Updated this week
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆27Updated 4 years ago
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆61Updated 2 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆67Updated 2 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆142Updated 10 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆56Updated this week
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆72Updated 10 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆61Updated 5 years ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆147Updated this week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆240Updated 5 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆59Updated 2 weeks ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 10 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆88Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆89Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆93Updated last year
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆31Updated 7 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆97Updated 4 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆185Updated this week
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆164Updated 4 months ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆47Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆140Updated last month
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆252Updated 2 weeks ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆99Updated 3 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆40Updated 13 years ago