facebookresearch / veripyLinks
VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, various code generation plugins and configurable code generation. The VeriPy Wiki has more the detailed documentation.
☆28Updated last month
Alternatives and similar repositories for veripy
Users that are interested in veripy are comparing it to the libraries listed below
Sorting:
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated 3 weeks ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆23Updated 6 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- Running Python code in SystemVerilog☆70Updated last month
- Systemverilog DPI-C call Python function☆25Updated 4 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Simple single-port AXI memory interface☆42Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 3 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆16Updated 5 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆10Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- hardware library for hwt (= ipcore repo)☆40Updated 3 weeks ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- A Python package for testing hardware (part of the magma ecosystem)☆43Updated last year
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆34Updated 3 weeks ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆61Updated 2 weeks ago
- Raptor end-to-end FPGA Compiler and GUI☆83Updated 7 months ago
- ☆96Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 6 months ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆45Updated 4 years ago
- Library of open source Process Design Kits (PDKs)☆48Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Python interface for cross-calling with HDL☆34Updated last month
- ☆30Updated last week
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year