Alternatives and similar repositories for AwesomeRISC-VResources

Users that are interested in AwesomeRISC-VResources are comparing it to the libraries listed below

• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆314Updated 10 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆457Updated this week
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆312Updated 2 weeks ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆398Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆631Updated 2 weeks ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆481Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆288Updated 2 weeks ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆578Updated 2 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆223Updated last month
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆198Updated 4 years ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆302Updated 2 years ago
• rafaelcalcada / rvx
  Open-source RISC-V microcontroller for embedded and FPGA applications
  ☆189Updated this week
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆232Updated this week
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆82Updated last week
• mattvenn / awesome-opensource-asic-resources
  ☆368Updated 2 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated 3 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆753Updated last month
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆370Updated 10 months ago
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆284Updated 7 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆754Updated 3 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆250Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 4 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆691Updated 2 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆629Updated last week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated last month
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆257Updated 2 weeks ago