Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
☆37Jun 30, 2024Updated 2 years ago
Alternatives and similar repositories for eda-scripts
Users that are interested in eda-scripts are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆12Sep 4, 2023Updated 3 years ago
- ☆11Jul 12, 2023Updated 3 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Apr 20, 2018Updated 8 years ago
- ☆20Dec 15, 2022Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Mastering FPGASIC Book☆19Oct 26, 2025Updated 10 months ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 10 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Updated this week
- Everything needed for ulx3s FPGA☆15Oct 12, 2020Updated 5 years ago
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Web-based HDL diagramming tool☆87May 1, 2023Updated 3 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆38Updated this week
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago
- Doxygen with verilog support☆41Mar 15, 2019Updated 7 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- C# projects that use ANTLR4 library to analyse VHDL and Verilog code☆11Feb 28, 2015Updated 11 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 5 months ago
- wifi☆12Jun 13, 2017Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 12 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- Hardware Trojan on a Basis 3 FPGA for Hardware and Embedded Systems Security☆11May 1, 2017Updated 9 years ago
- Drawio => VHDL and Verilog☆62Oct 15, 2023Updated 2 years ago
- QuSoC demo projects and template☆24Mar 4, 2026Updated 6 months ago
- Forward the UDP packages (like what NAT does) and do a simple Xor operation bytes by bytes.☆11Feb 18, 2020Updated 6 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆163Feb 27, 2025Updated last year
- Репозиторий канала Verification For All☆15May 27, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SDSoC platforms for Digilent Zynq boards☆11Mar 2, 2017Updated 9 years ago
- Generate and verify JWT tokens with Trusted Platform Module (TPM)☆15May 26, 2026Updated 3 months ago
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 7 years ago
- ☆44Mar 9, 2026Updated 6 months ago
- Multi-platform nightly builds of open source FPGA tools☆306Nov 3, 2021Updated 4 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆16Jul 7, 2024Updated 2 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago