miet-mpsu-dsp / labsView external linksLinks
Лабораторные работы по ЦОС (python)
☆10Apr 28, 2025Updated 9 months ago
Alternatives and similar repositories for labs
Users that are interested in labs are comparing it to the libraries listed below
Sorting:
- Материалы по курсу Углубленное изучение языка С (факультатив) для студентов МИЭТ☆12Feb 4, 2025Updated last year
- Методические материалы курса "Практикум по ПЛИС"☆41Updated this week
- Архитектуры процессорных систем (старый репозиторий, ранее размещавшийся по адресу github.com/MPSU/APS)☆97Jan 27, 2024Updated 2 years ago
- Методические материалы к лабораторным работам дисциплины "Проектирование цифровых устройств на языке Verilog"☆12Sep 4, 2023Updated 2 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆23Dec 5, 2024Updated last year
- Методические материалы по разработке процессора архитектуры RISC-V☆308Updated this week
- Открытый ознакомительный курс "Введение в функциональную верификацию RISC-V ядер"☆47Nov 7, 2025Updated 3 months ago
- ☆17Dec 20, 2025Updated last month
- list of links to resources related to functional verification☆12Sep 10, 2023Updated 2 years ago
- A mini development environment for developing and troubleshooting the Cypress PSoC Digital Filter Block☆11Mar 23, 2020Updated 5 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Feb 9, 2026Updated last week
- SystemVerilog language-oriented exercises☆57Jan 30, 2026Updated 2 weeks ago
- A tool to run litmus tests on bare-metal hardware☆13Mar 13, 2017Updated 8 years ago
- ☆11Jul 12, 2023Updated 2 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆15Apr 25, 2020Updated 5 years ago
- GNURadio implementation of the lazy Viterbi algorithm☆13May 8, 2020Updated 5 years ago
- A simple logging framework for Matlab, built on top of SLF4J and Log4j☆11Mar 16, 2023Updated 2 years ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆13Jul 7, 2024Updated last year
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆16Jan 7, 2026Updated last month
- Mad intensive course from Moscow campus of intra42☆11Jul 3, 2022Updated 3 years ago
- This asset allows you to set custom icons for any folder in unity project browser.☆14Dec 2, 2020Updated 5 years ago
- ☆15Feb 5, 2026Updated last week
- ☆15Apr 1, 2025Updated 10 months ago
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Формирование спецификации, перечня элементов и ведомости покупных изделий по ЕСКД из Altium и KiCad☆12Jun 18, 2025Updated 7 months ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 3 years ago
- Binary Coded Decimal. Research project for use with SQL_NUMERIC_STRUCT datatype☆13May 4, 2025Updated 9 months ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Simple pin assignment generator for IC case☆19Feb 14, 2017Updated 9 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated last week
- ☆17Jan 21, 2026Updated 3 weeks ago
- LiteX-based gateware for LimeSDR boards.☆18Updated this week
- An open-source Verilog implementation of Serial Peripheral Interface protocol with simulation support for efficient data exchange.☆14Dec 26, 2023Updated 2 years ago
- licenseMonitor is used to check instant EDA license information.☆28Aug 11, 2025Updated 6 months ago
- https://gpuzelenograd.github.io/☆13Jul 25, 2025Updated 6 months ago
- Advanced and fast log explorer with support to JSON files and columns☆19Jan 11, 2026Updated last month
- Synchronous Slave FIFO Interface between Xilinx Spartan 3E and Cypress FX3☆15Mar 11, 2015Updated 10 years ago
- Configurable and extensible logging for MATLAB applications☆18Aug 26, 2025Updated 5 months ago