Alternatives and similar repositories for quard-star-tutorial-2021

Users that are interested in quard-star-tutorial-2021 are comparing it to the libraries listed below

• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆21Updated 6 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆45Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆40Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last month
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 10 months ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆45Updated 2 years ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆19Updated 9 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 8 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆192Updated last year
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆70Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆166Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated 3 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆35Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆17Updated 4 years ago
• Jpz-sdju / trinity
  ☆32Updated 5 months ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated last year
• miaochenlu / learn_prefetcher
  hardware & software prefetcher
  ☆29Updated 2 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated last week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated last week
• Tanggling / BOOMCore
  This is a project created and completed by team BOOM(Beihang OO masters).This is a superscalar processor with a 13-stage out-of-order dua…
  ☆17Updated last year
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆43Updated last month
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 3 years ago