Alternatives and similar repositories for quard-star-tutorial-2021

Users that are interested in quard-star-tutorial-2021 are comparing it to the libraries listed below

• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆18Updated 2 months ago
• USTC-System-Courses / CECS-Lab
  ☆38Updated last year
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 5 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated last year
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆41Updated 2 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• mytbk / gem5-docs
  gem5 相关中文笔记
  ☆15Updated 3 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆176Updated 9 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆38Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 10 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• chipsalliance / rvdecoderdb
  The Scala parser to parse riscv/riscv-opcodes generate
  ☆21Updated last month
• josecm / riscv-hyp-tests
  A bare-metal application to test specific features of the risc-v hypervisor extension
  ☆40Updated last year
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• miaochenlu / Gem5_tutorials
  ☆20Updated 2 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆87Updated 2 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆44Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆64Updated this week
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆91Updated last year
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago