ee-uet / UETRV-PCoreLinks
Linux Capable 32-bit RISC-V based SoC in System Verilog
☆60Updated last month
Alternatives and similar repositories for UETRV-PCore
Users that are interested in UETRV-PCore are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- The multi-core cluster of a PULP system.☆111Updated last week
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆153Updated last year
- Simple runtime for Pulp platforms☆50Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆76Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆190Updated 3 months ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆72Updated last year
- RISC-V Nox core☆71Updated 5 months ago
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- RISC-V System on Chip Template☆160Updated 4 months ago
- ☆89Updated 4 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆252Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆104Updated 8 months ago
- PCI Express controller model☆71Updated 3 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆116Updated 5 months ago
- RISC-V Verification Interface☆136Updated last month
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆108Updated 3 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 5 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆76Updated last month
- A RISC-V Core (RV32I) written in Chisel HDL☆106Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆134Updated this week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated last month