Alternatives and similar repositories for arch_sec_papers

Users that are interested in arch_sec_papers are comparing it to the libraries listed below

• vusec / tlbdr
  ☆18Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 8 months ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 3 months ago
• MATCHA-MIT / Pensieve
  This repository provides Pensieve, a security evaluation framework for microarchitectural defenses against speculative execution attacks.
  ☆23Updated last year
• Compass-All / Raft
  Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V
  ☆10Updated last year
• FPSG-UIUC / Pandora
  Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data
  ☆20Updated 2 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• miaochenlu / Gem5_tutorials
  ☆20Updated this week
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆13Updated last year
• FPSG-UIUC / augury
  Using Data Memory-Dependent Prefetchers to Leak Data at Rest
  ☆36Updated 2 years ago
• zzrcxb / PinnedLoads
  Gem5 implementation of Pinned Loads: Taming Speculative Loads in Secure Processors
  ☆9Updated 2 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆17Updated last week
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• mktrm / SecSMT_Artifact
  The artifact for SecSMT paper -- Usenix Security 2022
  ☆27Updated 2 years ago
• riscv-admin / uarch-side-channels
  ☆16Updated 6 months ago
• riscv / riscv-memory-tagging
  Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
  ☆15Updated this week
• IPADS-DuVisor / kvm-tutorial
  ☆23Updated last year
• sycuricon / MorFuzz
  Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
  ☆29Updated last month
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆19Updated 3 months ago
• cispa / hammulator
  Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)
  ☆17Updated last year
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆14Updated this week
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• cwfletcher / stt
  ☆35Updated 4 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• scy-phy / FetchBench
  ☆17Updated last year
• Compass-All / CCS22-StrongBox
  ☆32Updated 2 years ago