IC Verification & SV Demo
☆59Sep 29, 2021Updated 4 years ago
Alternatives and similar repositories for AHB-SRAMC
Users that are interested in AHB-SRAMC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- ahb scram controller, design and verification☆29Jun 20, 2018Updated 7 years ago
- ☆26Aug 10, 2023Updated 2 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆198Jul 23, 2018Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Simple sram controller in verilog.☆36Jun 5, 2016Updated 9 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- 数字IC验证案例（SV and UVM）☆30Apr 27, 2021Updated 5 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 8 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆19Apr 27, 2024Updated 2 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆19Mar 6, 2020Updated 6 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An uvm verification env for ahb2apb bridge☆58Apr 9, 2021Updated 5 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- AMBA bus lecture material☆532Jan 21, 2020Updated 6 years ago
- ☆22Sep 26, 2025Updated 7 months ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆33Jul 4, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆12Mar 10, 2023Updated 3 years ago
- ☆19Apr 28, 2026Updated last week
- Modular Multi-ported SRAM-based Memory☆32Nov 8, 2024Updated last year
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 6 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆20May 30, 2023Updated 2 years ago
- This is for uvm_tb_gen☆53Feb 13, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Mirror of william_william/uvm-mcdf on Gitee☆33Nov 30, 2022Updated 3 years ago
- ☆38Mar 10, 2021Updated 5 years ago
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆27Mar 5, 2026Updated 2 months ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆47Mar 3, 2024Updated 2 years ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆24Jun 30, 2025Updated 10 months ago