wangjidwb123 / AHB-SRAMC
IC Verification & SV Demo
☆52Updated 3 years ago
Alternatives and similar repositories for AHB-SRAMC:
Users that are interested in AHB-SRAMC are comparing it to the libraries listed below
- AXI总线连接器☆95Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 2 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆21Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is …☆58Updated last year
- 数字IC秋招项目、手撕代码☆34Updated 10 months ago
- An uvm verification env for ahb2apb bridge☆48Updated 3 years ago
- ☆18Updated 5 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆111Updated 7 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆165Updated 6 years ago
- AXI Interconnect☆47Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆85Updated last year
- VIP for AXI Protocol☆122Updated 2 years ago
- UVM AHB VIP☆80Updated 3 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆56Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆34Updated 2 years ago
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- ☆59Updated 9 years ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- ☆36Updated 9 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆100Updated 2 months ago