Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
☆15Feb 18, 2025Updated last year
Alternatives and similar repositories for EF_UART
Users that are interested in EF_UART are comparing it to the libraries listed below
Sorting:
- Verification IP for UART protocol☆23Aug 3, 2020Updated 5 years ago
- ☆11May 8, 2022Updated 3 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- A complete UVM TB for verification of single port 64KB RAM☆17Apr 16, 2021Updated 4 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆30Nov 3, 2025Updated 3 months ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Apr 24, 2019Updated 6 years ago
- RISCV CPU implementation in SystemVerilog☆32Oct 1, 2025Updated 5 months ago
- UART implementation using verilog☆33Feb 14, 2023Updated 3 years ago
- ☆34Feb 17, 2026Updated last week
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆60Aug 9, 2020Updated 5 years ago
- Verification IP for APB protocol☆33Sep 9, 2020Updated 5 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Dec 1, 2022Updated 3 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Simulating implement of LeNet network on Zynq-7020 FPGA☆30Mar 11, 2019Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Verilog implementation of various types of CPUs☆76Sep 27, 2019Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- UVM AHB VIP☆94Sep 13, 2025Updated 5 months ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Jun 19, 2020Updated 5 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- A 16-bit RISC-V Inspired ISA☆23Jul 19, 2025Updated 7 months ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- LLM-DSE: Searching Accelerator Parameters with LLM Agents☆13May 22, 2025Updated 9 months ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago