efabless / EF_UARTLinks
Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
☆13Updated 8 months ago
Alternatives and similar repositories for EF_UART
Users that are interested in EF_UART are comparing it to the libraries listed below
Sorting:
- Verification IP for Watchdog☆11Updated 4 years ago
- ☆20Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆18Updated 11 years ago
- ☆16Updated 6 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆28Updated 9 months ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- ☆12Updated 10 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆15Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆11Updated 3 years ago
- To design test bench of the APB protocol☆18Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Verification IP for UART protocol☆20Updated 5 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆29Updated last year
- ☆21Updated 6 years ago
- ☆17Updated 10 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Updated 7 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- Various low power labs using sky130☆13Updated 4 years ago
- ☆26Updated 4 years ago