visky2096 / AHB-to-I2CView external linksLinks
Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C master and I2c slave. The RTL and all the test benches are written in [VERILOG]
☆22Feb 25, 2019Updated 6 years ago
Alternatives and similar repositories for AHB-to-I2C
Users that are interested in AHB-to-I2C are comparing it to the libraries listed below
Sorting:
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- APB to I2C☆43Jul 17, 2014Updated 11 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- ☆18Aug 11, 2022Updated 3 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- General Purpose IO with APB4 interface☆14May 10, 2024Updated last year
- ☆11Mar 10, 2023Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆32Feb 7, 2025Updated last year
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆21Sep 26, 2025Updated 4 months ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆17Oct 6, 2024Updated last year
- ☆20Aug 22, 2022Updated 3 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆39Jun 27, 2021Updated 4 years ago
- round robin arbiter☆78Jul 17, 2014Updated 11 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- A CIC filter implemented in Verilog☆25Sep 7, 2015Updated 10 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Jan 14, 2018Updated 8 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 7 years ago
- A simple UVM example with DPI☆45Aug 7, 2017Updated 8 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated last year
- ☆20Nov 18, 2022Updated 3 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆20Apr 11, 2022Updated 3 years ago
- amba3 apb/axi vip☆53Feb 24, 2015Updated 10 years ago
- VIP for AXI Protocol☆164May 24, 2022Updated 3 years ago
- AHB DMA 32 / 64 bits☆59Jul 17, 2014Updated 11 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 6 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- An uvm verification env for ahb2apb bridge☆58Apr 9, 2021Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆30Jun 1, 2022Updated 3 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆31Jul 4, 2024Updated last year
- Verification IP for APB protocol☆75Dec 18, 2020Updated 5 years ago
- systemc建模相关☆28Jun 11, 2014Updated 11 years ago