Alternatives and similar repositories for AHB-to-I2C

Users that are interested in AHB-to-I2C are comparing it to the libraries listed below

• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 10 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆53Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆14Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆49Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• freecores / apbi2c
  APB to I2C
  ☆41Updated 10 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 3 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆15Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆33Updated 2 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆17Updated 10 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• somyadashora / AMBA-AXI4-Lite
  Master and Slave made using AMBA AXI4 Lite protocol.
  ☆26Updated 4 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆13Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 10 years ago
• designsolver / ahb2apb_bridge_vip
  AHB to APB Bridge VIP
  ☆29Updated 6 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 4 months ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆32Updated 5 years ago
• Verdvana / AXI_SRAM
  支持AXI总线协议的8k×8 SP SRAM
  ☆25Updated 5 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 2 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆31Updated 3 years ago