visky2096 / AHB-to-I2CLinks
Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C master and I2c slave. The RTL and all the test benches are written in [VERILOG]
☆22Updated 6 years ago
Alternatives and similar repositories for AHB-to-I2C
Users that are interested in AHB-to-I2C are comparing it to the libraries listed below
Sorting:
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆27Updated 8 months ago
- Verification IP for APB protocol☆71Updated 4 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Maven Silicon Project☆19Updated 7 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- ☆26Updated 4 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- An uvm verification env for ahb2apb bridge☆56Updated 4 years ago
- a very simple risc_cpu verification demo with uvm☆26Updated 6 years ago
- Verification IP for I2C protocol☆49Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- AXI Interconnect☆53Updated 4 years ago
- Verification IP for SPI protocol☆20Updated 5 years ago
- Verification IP for APB protocol☆29Updated 5 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆14Updated 4 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- ☆20Updated 2 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- AHB to APB Bridge VIP☆29Updated 6 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆46Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- ☆43Updated last year
- Simple AMBA VIP, Include axi/ahb/apb☆27Updated last year
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- APB to I2C☆43Updated 11 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆51Updated 5 years ago
- ☆38Updated 10 years ago