Alternatives and similar repositories for mips-cpu

Users that are interested in mips-cpu are comparing it to the libraries listed below

• stevehoover / makerchip_examples
  ☆19Updated 2 weeks ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆26Updated 4 years ago
• diadatp / mips_cpu
  A implementation of a 32-bit single cycle MIPS processor in Verilog.
  ☆20Updated 4 years ago
• nickson-jose / openlane_build_script
  This script builds openlane and all its dependencies on an Ubuntu (only) System.
  ☆21Updated 3 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• freecores / simple_spi
  SPI core
  ☆12Updated 11 years ago
• vsdip / rvmyth_avsddac_interface
  ☆14Updated 3 years ago
• freecores / pci
  PCI bridge
  ☆18Updated 11 years ago
• freecores / sgmii
  SGMII
  ☆13Updated 11 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆30Updated 3 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆27Updated 3 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 9 months ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆31Updated 9 months ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆52Updated 5 years ago
• freecores / reed_solomon_decoder
  Reed Solomon Decoder (204,188)
  ☆12Updated 11 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 7 months ago
• supratimdas / NoobsCpu-8bit
  A simple 8bit CPU.
  ☆26Updated 8 months ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆14Updated 5 months ago
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆28Updated 7 years ago
• shrut1996 / Cache-Implementation
  Implementation of a cache memory in verilog
  ☆14Updated 7 years ago
• merldsu / PY_UVM_Framework
  This repo contain the PY-UVM Framework for different RISC-V Cores
  ☆32Updated last year
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆104Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 6 months ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆94Updated last week
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆20Updated 4 years ago
• mbits-mirafra / UVMCourse
  Structured UVM Course
  ☆47Updated last year