ahegazy / mips-cpu
A verilog implementation of MIPS ISA.
☆18Updated 5 years ago
Alternatives and similar repositories for mips-cpu:
Users that are interested in mips-cpu are comparing it to the libraries listed below
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆21Updated 6 years ago
- ☆18Updated this week
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆11Updated 3 years ago
- ☆17Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆19Updated 3 years ago
- A simple 8bit CPU.☆25Updated 4 months ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- ☆12Updated 9 months ago
- Generic AXI master stub☆19Updated 10 years ago
- Various low power labs using sky130☆12Updated 3 years ago
- Structured UVM Course☆40Updated last year
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆30Updated 2 years ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆19Updated 4 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 3 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆42Updated 4 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆23Updated 6 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- M-extension for RISC-V cores.☆30Updated 5 months ago
- fpga verilog risc-v rv32i cpu☆11Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆26Updated 13 years ago