ahegazy / mips-cpuLinks
A verilog implementation of MIPS ISA.
☆18Updated 6 years ago
Alternatives and similar repositories for mips-cpu
Users that are interested in mips-cpu are comparing it to the libraries listed below
Sorting:
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆20Updated 5 years ago
- ☆19Updated last month
- RISC V core implementation using Verilog.☆28Updated 4 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆23Updated 3 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- Platform Level Interrupt Controller☆44Updated last year
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated 2 years ago
- ☆15Updated 4 years ago
- ☆24Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Updated last year
- A simple 8bit CPU.☆26Updated last year
- Simple strutured VERILOG netlist to SPICE netlist translator☆25Updated 3 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Updated 11 years ago
- SPI core☆12Updated 11 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 4 years ago
- An open source CPU design and verification platform for academia☆116Updated 5 months ago
- Extended and external tests for Verilator testing☆17Updated 2 weeks ago
- fpga verilog risc-v rv32i cpu☆14Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- A Verilog implementation of a processor cache.☆35Updated 8 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆41Updated 4 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆32Updated 7 years ago
- My local copy of UVM-SystemC☆14Updated last year
- ☆19Updated 3 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago