☆38Jun 20, 2026Updated last week
Alternatives and similar repositories for docs-spec-template
Users that are interested in docs-spec-template are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆50May 22, 2026Updated last month
- RISC-V RV32IM cpu circuit in Logisim Evolution.☆27Jun 9, 2021Updated 5 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库！☆18May 9, 2024Updated 2 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆24Nov 21, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Neural Markov Logic Networks☆13Feb 14, 2022Updated 4 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- An almost empty chisel project as a starting point for hardware design☆36Jan 27, 2025Updated last year
- Source for openrisc.io☆13Jun 29, 2025Updated last year
- WISHBONE Builder☆15Sep 10, 2016Updated 9 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- An implementation of the Advanced Encryption Standard (AES) encryption algorithm using Verilog supporting AES-128, AES-192, and AES-256 e…☆14Jun 7, 2025Updated last year
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆26Oct 15, 2025Updated 8 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- OSCAR main source repository.☆16Sep 25, 2025Updated 9 months ago
- Official implementation of "Discover network dynamics with neural symbolic regression"☆54Jan 6, 2026Updated 5 months ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆21May 4, 2017Updated 9 years ago
- SRAM build space for SKY130 provided by SkyWater.☆25Oct 20, 2021Updated 4 years ago
- ☆16Apr 21, 2019Updated 7 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- USB 1.1 PHY☆11Jul 17, 2014Updated 11 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- An open-source Simulation Trace Format specification☆17Jun 4, 2026Updated 3 weeks ago
- ePIC (Embedded PIC) example: kernel and relocatable loadable app☆14Oct 27, 2023Updated 2 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆37Oct 23, 2025Updated 8 months ago
- The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…☆23Jun 22, 2026Updated last week
- RISC-V architecture concurrency model litmus tests☆104May 20, 2026Updated last month
- Arizona State University CSE320☆13Mar 22, 2015Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AES-128 Encryption☆11Jul 17, 2014Updated 11 years ago
- 白盒CLEFIA加密算法☆14Mar 30, 2016Updated 10 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 6 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- A base container image populated with the dependencies to build the RISC-V Documentation.☆22Jun 22, 2026Updated last week
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 5 years ago
- All Digital Phase-Locked Loop☆14May 22, 2023Updated 3 years ago