Groupsun / riscv-mini-five-stage
This is my graduation project, a simple processor soft core, which implements RV32I ISA.
☆14Updated 5 years ago
Alternatives and similar repositories for riscv-mini-five-stage:
Users that are interested in riscv-mini-five-stage are comparing it to the libraries listed below
- ☆61Updated 6 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆137Updated 4 months ago
- ☆53Updated last month
- A RISC-V RV32I ISA Single Cycle CPU☆22Updated last year
- ☆79Updated this week
- ☆57Updated last year
- 一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆25Updated 2 years ago
- "aura" my super-scalar O3 cpu core☆24Updated 8 months ago
- ☆20Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆47Updated 2 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆122Updated 7 months ago
- 我的一生一芯项目☆16Updated 3 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆28Updated 10 months ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆30Updated 2 weeks ago
- Pick your favorite language to verify your chip.☆37Updated last month
- 一生一芯项目☆11Updated last year
- ☆63Updated 2 years ago
- ☆59Updated last week
- ☆17Updated last year
- MIT6.175 & MIT6.375 Study Notes☆32Updated last year
- Unofficial guide for ysyx students applying to ShanghaiTech University☆20Updated 7 months ago
- Open IP in Hardware Description Language.☆18Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆46Updated last year
- Modern co-simulation framework for RISC-V CPUs☆132Updated this week
- NUDT 高级体系结构实验☆31Updated 4 months ago
- ☆74Updated this week
- ☆38Updated 2 years ago
- a simple riscv cpu☆22Updated 2 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆37Updated last year