This is my graduation project, a simple processor soft core, which implements RV32I ISA.
☆16May 23, 2019Updated 6 years ago
Alternatives and similar repositories for riscv-mini-five-stage
Users that are interested in riscv-mini-five-stage are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CPU source code for NSCSCC 2023☆14Aug 26, 2023Updated 2 years ago
- writing c compiler in rust. inspired by https://www.sigbus.info/compilerbook☆14Jul 11, 2021Updated 4 years ago
- ☆31Apr 10, 2026Updated 3 weeks ago
- The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.☆45Apr 11, 2021Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated 2 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖☆16Aug 17, 2024Updated last year
- Build script to compile an up-to-date RISC-V GCC toolchain on Debian / Ubuntu with rv32e, rv32i and rv64i architectures and ilp32e, ilp3…☆11Aug 5, 2025Updated 9 months ago
- Simple RISC-V 3-stage Pipeline in Chisel☆608Aug 9, 2024Updated last year
- Baremetal softwares for TrivialMIPS platform☆11Aug 12, 2019Updated 6 years ago
- ☆17Jul 31, 2024Updated last year
- ☆13May 8, 2025Updated last year
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- Support Repository of "How to make RISC-V Microcomputer using FPGA for programmer"☆18Jul 30, 2019Updated 6 years ago
- A simple 5-stage Pipeline RISC-V core☆19Jun 8, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆67Aug 5, 2024Updated last year
- ☆77Apr 23, 2023Updated 3 years ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆24Sep 14, 2024Updated last year
- An almost empty chisel project as a starting point for hardware design☆36Jan 27, 2025Updated last year
- 顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel☆29Jan 25, 2026Updated 3 months ago
- 2024年第八届龙芯杯 LA 个人赛二等奖参赛作品☆25Aug 20, 2024Updated last year
- 基于Golang实现的最轻量级文件传 输工具、个人临时网盘☆11May 13, 2022Updated 3 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- all kind of notes, I maybe sort this in the future☆13Aug 29, 2025Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆68Apr 29, 2026Updated last week
- A framework for ysyx flow☆14Oct 31, 2024Updated last year
- Scripts to automate building linux images for my emulator riscv_em☆16Oct 24, 2023Updated 2 years ago
- 基于小脚丫FPGA的电子琴，模拟钢琴音色，支持127个音符演奏，可通过转化MIDI文件实现自动播放☆16Aug 22, 2022Updated 3 years ago
- 基4booth乘法器设计与验证☆15Apr 28, 2024Updated 2 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- A RISC-V Core (RV32I) written in Chisel HDL☆108Feb 3, 2026Updated 3 months ago
- 哈尔滨工业大学数字逻辑与数字系统设计课程大作业——电子密码锁设计部分代码（2020秋）☆14Jan 18, 2021Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated last year
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆78Jan 15, 2023Updated 3 years ago
- NYU's fork of MIT's xv6-public☆15Dec 10, 2023Updated 2 years ago
- Rust library for low-level abstraction of MIPS processors☆31Jun 6, 2020Updated 5 years ago
- An exquisite superscalar RV32GC processor.☆170Apr 15, 2026Updated 3 weeks ago
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated last year