NayanaBannur / 8-bit-RISC-ProcessorLinks
A Verilog RTL model of a simple 8-bit RISC processor
☆14Updated 6 years ago
Alternatives and similar repositories for 8-bit-RISC-Processor
Users that are interested in 8-bit-RISC-Processor are comparing it to the libraries listed below
Sorting:
- FIFO implementation with different clock domains for read and write.☆13Updated 4 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆12Updated 4 years ago
- Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture☆12Updated 5 years ago
- A Tiny Processor Core☆110Updated last month
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆93Updated 5 months ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆24Updated last year
- An implementation of RISC-V☆39Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆73Updated last year
- Verilog implementation of a RISC-V core☆124Updated 6 years ago
- MR1 formally verified RISC-V CPU☆53Updated 6 years ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆150Updated 10 months ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 5 months ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Lipsi: Probably the Smallest Processor in the World☆86Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆53Updated last year
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆75Updated 2 years ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆26Updated 6 years ago
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆74Updated 3 weeks ago
- Learn RISC-V☆21Updated 9 months ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- FreeRTOS port for the RISC-V Virtual Prototype☆14Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 5 months ago
- The multi-core cluster of a PULP system.☆108Updated this week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Naive Educational RISC V processor☆88Updated last month
- ☆24Updated 8 years ago
- RISC-V System on Chip Template☆159Updated 2 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- 64-bit multicore Linux-capable RISC-V processor☆96Updated 4 months ago