Alternatives and similar repositories for 8-bit-RISC-Processor

Users that are interested in 8-bit-RISC-Processor are comparing it to the libraries listed below

• schoeberl / wildcat
  An implementation of RISC-V
  ☆44Updated last week
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated last year
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆13Updated 4 years ago
• ZiCog / sodor-spinal
  An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.
  ☆14Updated 6 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 5 months ago
• Charlie5DH / RISC-V-Single-Cycle-uP
  Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
  ☆12Updated 5 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• pulp-platform / apb_timer
  APB Timer Unit
  ☆13Updated last month
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆70Updated 4 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆106Updated 4 years ago
• agra-uni-bremen / riscv-freertos
  FreeRTOS port for the RISC-V Virtual Prototype
  ☆14Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆70Updated 3 years ago
• odedyo / Median-filter-verilog-
  Design a median filter for a Generic RGB image.
  ☆14Updated 6 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆51Updated last year
• digital-design-hq / Digital-Resources
  ☆63Updated 4 years ago
• AngeloJacobo / FPGA_Asynchronous_FIFO
  FIFO implementation with different clock domains for read and write.
  ☆14Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 9 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 5 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated 2 weeks ago
• phoeniX-Digital-Design / phoeniX
  A Reconfigurable RISC-V Core for Approximate Computing
  ☆128Updated 6 months ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• sjohann81 / hf-risc
  HF-RISC SoC
  ☆39Updated last month
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆26Updated 6 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆160Updated 9 months ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆76Updated 2 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆129Updated 2 months ago