NayanaBannur / 8-bit-RISC-Processor

Related projects ⓘ

Alternatives and complementary repositories for 8-bit-RISC-Processor

• schoeberl / wildcat
  An implementation of RISC-V
  ☆16Updated 3 weeks ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆40Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆66Updated this week
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆20Updated 5 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆56Updated last week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆68Updated 11 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆53Updated 2 weeks ago
• aignacio / nox
  RISC-V Nox core
  ☆61Updated 3 months ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆42Updated 3 weeks ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆51Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 6 months ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆102Updated 6 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆59Updated last month
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆40Updated this week
• AngeloJacobo / FPGA_Asynchronous_FIFO
  FIFO implementation with different clock domains for read and write.
  ☆13Updated 3 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆101Updated 3 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆51Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆89Updated 3 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 11 months ago
• verilator / example-systemverilog
  ☆34Updated 9 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆81Updated 7 months ago
• vfinotti / cortex-m0-soft-microcontroller
  Soft-microcontroller implementation of an ARM Cortex-M0
  ☆23Updated 5 years ago
• riscveval / Rocket-Chip
  ☆21Updated 7 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆64Updated 2 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆22Updated this week
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆78Updated 3 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆63Updated 7 months ago