NayanaBannur / 8-bit-RISC-Processor
A Verilog RTL model of a simple 8-bit RISC processor
☆12Updated 6 years ago
Alternatives and similar repositories for 8-bit-RISC-Processor:
Users that are interested in 8-bit-RISC-Processor are comparing it to the libraries listed below
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆22Updated 6 months ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆10Updated 3 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆57Updated last month
- Open source ISS and logic RISC-V 32 bit project☆41Updated last month
- Soft-microcontroller implementation of an ARM Cortex-M0☆24Updated 5 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆43Updated last year
- An implementation of RISC-V☆20Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 7 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆76Updated last year
- ☆54Updated 3 years ago
- RISC-V Nox core☆62Updated 5 months ago
- A pipelined RISC-V processor☆48Updated last year
- A Tiny Processor Core☆104Updated 2 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆84Updated 5 years ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆79Updated last year
- Verilog implementation of a RISC-V core☆107Updated 6 years ago
- This repository is created for conducting RISC-V 5-day workshops☆22Updated 4 years ago
- ☆18Updated last year
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆16Updated last year
- SoftCPU/SoC engine-V☆54Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆29Updated 3 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆28Updated 3 years ago
- ☆11Updated 6 months ago
- A simple implementation of a UART modem in Verilog.☆115Updated 3 years ago
- Simple 8-bit UART realization on Verilog HDL.☆93Updated 8 months ago
- ☆33Updated 2 years ago
- ☆35Updated 11 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆62Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 2 years ago