Alternatives and similar repositories for VerilogLanguageExtension

Users that are interested in VerilogLanguageExtension are comparing it to the libraries listed below

• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• sparrowgrine / prjtritium
  ☆22Updated 3 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• betrusted-io / gateware
  IP submodules, formatted for easier CI integration
  ☆30Updated last year
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆30Updated 2 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆55Updated 2 years ago
• azonenberg / jtaghal
  JTAG Hardware Abstraction Library
  ☆36Updated last year
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• antonblanchard / ghdl-yosys-blink
  Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr
  ☆26Updated 5 years ago
• jevinskie / liteluna
  LiteX LUNA USB stack integration
  ☆14Updated 3 years ago
• ulixxe / usb_dfu
  Full Speed USB DFU interface for FPGA and ASIC designs
  ☆19Updated last year
• hedgeberg / VerilogCommon
  A repo of basic Verilog/SystemVerilog modules useful in other circuits.
  ☆21Updated 7 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆31Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 3 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• GuzTech / shdl6800
  shdl6800: A 6800 processor written in SpinalHDL
  ☆26Updated 5 years ago
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 4 years ago
• mattvenn / vga-clock
  Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
  ☆62Updated 3 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• emard / esp32ecp5
  micropython ESP32 programmer/flasher for ECP5 JTAG
  ☆71Updated last month
• j-marjanovic / ocs-tray-mezzanine-adapter
  PCIe adapter for an FPGA accelerator for Open CloudServer
  ☆23Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆60Updated 2 weeks ago
• ultraembedded / riscv_sbc
  A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
  ☆29Updated 5 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆39Updated 5 years ago
• smunaut / iua
  ice40 USB Analyzer
  ☆58Updated 4 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆92Updated 5 years ago
• no2fpga / no2muacm
  Drop In USB CDC ACM core for iCE40 FPGA
  ☆34Updated 3 years ago