pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
☆19Updated last year
Alternatives and similar repositories for Design-of-various-multiplier-Array-Booth-Wallace-:
Users that are interested in Design-of-various-multiplier-Array-Booth-Wallace- are comparing it to the libraries listed below
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆27Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆14Updated 10 months ago
- Some useful documents of Synopsys☆67Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- AXI总线连接器☆96Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- AXI Interconnect☆47Updated 3 years ago
- ☆31Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆82Updated 5 years ago
- ☆16Updated 11 months ago
- ☆15Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .☆12Updated 6 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆16Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆34Updated 2 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- A verilog FPGA Interface for AXI4_Lite from Slave side☆11Updated 4 years ago