shobro / ACLALinks
Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
☆12Updated 3 years ago
Alternatives and similar repositories for ACLA
Users that are interested in ACLA are comparing it to the libraries listed below
Sorting:
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆15Updated 2 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆36Updated 6 years ago
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆77Updated last year
- Final project for Computer Architecture FA16☆18Updated 8 years ago
- ☆19Updated last year
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- A collection of commonly asked RTL design interview questions☆30Updated 8 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- Image processing on FPGA using verilog☆22Updated 2 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆23Updated 7 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆59Updated last year
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆40Updated last month
- Matrix Multiply and Accumulate unit written in System Verilog☆11Updated 6 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- ☆22Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 9 months ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- Digital Design verilog tricky problems having industry standards☆23Updated 4 years ago
- Verilog implementation of a pre-trained handwritten digit recognition simple neural network.☆20Updated last year
- Learn UVM by small projects☆10Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆27Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 2 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆36Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆24Updated 7 years ago