ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
2020 xilinx summer school
☆17Updated 4 years ago
Alternatives and similar repositories for Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA:
Users that are interested in Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA are comparing it to the libraries listed below
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated last year
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆24Updated 3 years ago
- ☆21Updated 2 years ago
- Codes to implement MobileNet V2 in a FPGA☆25Updated 4 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago
- cnn accelerator in vivado HLS☆9Updated 3 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 3 years ago
- ☆26Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 2 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- ☆20Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆29Updated 6 months ago
- A DNN Accelerator implemented with RTL.☆63Updated 3 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- Low-Precision YOLO on PYNQ with FINN☆31Updated last year
- Some attempts to build CNN on PYNQ.☆24Updated 5 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago