ZhangYuQAQ / Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGALinks
2020 xilinx summer school
☆18Updated 5 years ago
Alternatives and similar repositories for Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA
Users that are interested in Hardware-Acceleration-Circuit-Design-of-Object-Detection-Network-Based-on-FPGA are comparing it to the libraries listed below
Sorting:
- ☆21Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- ☆31Updated 7 months ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆26Updated 3 years ago
- Open-source of MSD framework☆16Updated 2 years ago
- A collection of tutorials for the fpgaConvNet framework.☆46Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆20Updated 3 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆27Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- ☆17Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- ☆35Updated 6 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆19Updated 6 years ago
- DAC System Design Contest 2020☆29Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆95Updated 4 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- ☆18Updated 2 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆39Updated 4 years ago
- ☆71Updated 5 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆52Updated 7 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Updated 5 years ago