twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
☆39Updated 3 years ago
Related projects: ⓘ
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆37Updated 5 years ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆29Updated 9 months ago
- VLSI EDA Global Router☆64Updated 6 years ago
- ☆24Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆75Updated 3 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆75Updated 10 months ago
- ☆67Updated 8 months ago
- Material for OpenROAD Tutorial at DAC 2020☆45Updated last year
- ☆17Updated last year
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆50Updated 4 years ago
- DATC RDF☆48Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆27Updated 3 weeks ago
- ☆26Updated 2 years ago
- ☆29Updated 11 months ago
- Open Source Detailed Placement engine☆32Updated 4 years ago
- ☆34Updated 5 months ago
- A LEF/DEF Utility.☆26Updated 5 years ago
- ☆76Updated 2 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆72Updated this week
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated 10 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆22Updated 4 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆92Updated 2 months ago
- An analytical VLSI placer☆25Updated 2 years ago
- Routing Visualization for Physical Design☆18Updated 5 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆44Updated 2 months ago
- EDA physical synthesis optimization kit☆49Updated 10 months ago
- Power grid analysis☆17Updated 4 years ago
- Artificial Netlist Generator☆29Updated 6 months ago
- Logic synthesis and ABC based optimization☆44Updated last week
- Source codes and calibration scripts for clock tree synthesis☆38Updated 4 years ago