laurentc2 / Verilog2SpiceLinks
Simple strutured VERILOG netlist to SPICE netlist translator
☆21Updated 3 years ago
Alternatives and similar repositories for Verilog2Spice
Users that are interested in Verilog2Spice are comparing it to the libraries listed below
Sorting:
- ☆41Updated 3 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆64Updated last month
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆73Updated 4 years ago
- KLayout technology files for Skywater SKY130☆40Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- LAYout with Gridded Objects☆29Updated 5 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆81Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- Skywater 130nm Klayout Device Generators PDK☆31Updated last year
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆67Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆36Updated 8 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- MOSIS MPW Test Data and SPICE Models Collections☆37Updated 5 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago
- ☆84Updated 6 months ago
- UW reference flow for Free45PDK and The OpenROAD Project☆11Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- Logic synthesis and ABC based optimization☆49Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- PLL Designs on Skywater 130nm MPW☆20Updated last year
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆121Updated 2 months ago
- Python Tool for UVM Testbench Generation☆53Updated last year
- Qrouter detail router for digital ASIC designs☆56Updated 3 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- Completed LDO Design for Skywaters 130nm☆14Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 6 months ago