Simple strutured VERILOG netlist to SPICE netlist translator
☆26May 22, 2022Updated 4 years ago
Alternatives and similar repositories for Verilog2Spice
Users that are interested in Verilog2Spice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆18Mar 28, 2025Updated last year
- Power grid analysis☆23Aug 5, 2020Updated 5 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Python interface for Cadence Spectre☆28Feb 17, 2026Updated 3 months ago
- This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL☆20Feb 23, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆25Jul 1, 2024Updated last year
- AES☆15Oct 4, 2022Updated 3 years ago
- AES-128 Encryption☆11Jul 17, 2014Updated 11 years ago
- LZW Compressoion algorithm in verilog☆17Dec 19, 2013Updated 12 years ago
- LTspice to Kicad schematic conversion☆35Oct 4, 2020Updated 5 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- ESP32-NOW with Wifi☆23Apr 11, 2025Updated last year
- ☆16Jan 8, 2022Updated 4 years ago
- UW reference flow for Free45PDK and The OpenROAD Project☆13Jun 5, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆21Aug 8, 2022Updated 3 years ago
- A tiny Python package to parse spice raw data files.☆53Dec 26, 2022Updated 3 years ago
- Parser and Viewer for Cadence® Library Exchange Format (LEF) and Design Exchange Format (DEF) integrated circuit (IC) description languag…☆17May 31, 2023Updated 3 years ago
- VeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation,…☆38May 20, 2026Updated 3 weeks ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 11 years ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- Acorn BBC Micro on an Altera DE1 FPGA board☆24Jan 13, 2016Updated 10 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A python library for ngspice☆15Apr 13, 2026Updated 2 months ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- An i2c master controller implemented in Verilog☆35Jul 26, 2017Updated 8 years ago
- ☆14Oct 8, 2024Updated last year
- Minix 1.5 source code for the Atari ST☆13Feb 8, 2016Updated 10 years ago
- Parasitic capacitance analysis of foundry metal stackups☆18Jan 12, 2026Updated 5 months ago
- ☆19Aug 30, 2020Updated 5 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆28Mar 21, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Instruction and files for porting Arm DesignStart to CW305.☆17Dec 6, 2023Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 9 years ago
- Python iterface for Cadence LEF/DEF parser.☆38Oct 31, 2023Updated 2 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆21Aug 20, 2019Updated 6 years ago
- [ICCAD'22 TinyML Contest] Efficient Heart Stroke Detection on Low-cost Microcontrollers☆16Jan 12, 2023Updated 3 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago