Alternatives and similar repositories for Verilog2Spice:

Users that are interested in Verilog2Spice are comparing it to the libraries listed below

• vsdip / vsdsram_sky130
  ☆40Updated 3 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• nickson-jose / openlane_build_script
  This script builds openlane and all its dependencies on an Ubuntu (only) System.
  ☆21Updated 2 years ago
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆44Updated 4 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆62Updated 3 weeks ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• OS-EDA / Course
  Home of the open-source EDA course.
  ☆37Updated last month
• sscs-ose / sscs-ose-chipathon.github.io
  ☆77Updated 3 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆90Updated this week
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆27Updated 4 years ago
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆11Updated 4 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆39Updated last year
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆53Updated 2 years ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆38Updated 3 years ago
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated last year
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆41Updated 3 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆68Updated 4 years ago
• akshaymdas / OpenLANE-SkyWater130-workshop
  This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…
  ☆22Updated 3 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆54Updated last year
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆74Updated this week
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 11 months ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆34Updated 5 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆55Updated 2 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆57Updated 2 years ago
• yellekelyk / PyVerilog
  Python-based Verilog Parser (currently Netlist only)
  ☆54Updated 8 years ago
• pulp-platform / svase
  ☆31Updated 3 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆65Updated last year
• vsdip / avsddac_3v3_sky130_v2
  ☆16Updated 2 years ago