natu4u / GSOC_TensorCore
TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
☆21Updated 3 years ago
Alternatives and similar repositories for GSOC_TensorCore:
Users that are interested in GSOC_TensorCore are comparing it to the libraries listed below
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆49Updated 3 years ago
- ☆23Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆26Updated 3 months ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆25Updated 2 weeks ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆31Updated 3 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Reconfigurable Binary Engine☆15Updated 3 years ago
- Learn NVDLA by SOMNIA☆30Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- ☆24Updated 5 years ago
- ☆40Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆25Updated last year
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆20Updated 5 months ago
- Algorithmic C Machine Learning Library☆22Updated last month
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated 10 months ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆9Updated 5 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆19Updated 2 months ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- course design☆22Updated 6 years ago
- ☆33Updated 3 years ago
- CNN accelerator☆27Updated 7 years ago