TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
☆25Aug 23, 2021Updated 4 years ago
Alternatives and similar repositories for GSOC_TensorCore
Users that are interested in GSOC_TensorCore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆63Dec 19, 2021Updated 4 years ago
- CK workflow, portable packages and other artifacts for the ReQuEST-ASPLOS'18 submission:☆12Jan 16, 2019Updated 7 years ago
- A NVDLA Loadable Parser.☆12Mar 2, 2022Updated 4 years ago
- 最小和算法实现☆10Jul 12, 2020Updated 5 years ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆19Apr 22, 2026Updated last week
- Analog and power building blocks for sky130 pdk☆22Mar 3, 2021Updated 5 years ago
- ☆16Oct 2, 2019Updated 6 years ago
- ☆23Dec 8, 2022Updated 3 years ago
- ☆12Apr 19, 2022Updated 4 years ago
- Aiming at an AI Chip based on RISC-V and NVDLA.☆21Mar 8, 2018Updated 8 years ago
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 9 years ago
- ☆33Mar 6, 2023Updated 3 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Dec 6, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- STONNE: A Simulation Tool for Neural Networks Engines☆152Jun 16, 2025Updated 10 months ago
- Automatic Test Pattern Generation using PODEM algorithm☆15May 12, 2014Updated 11 years ago
- APB Logic☆25Feb 24, 2026Updated 2 months ago
- SRAM☆24Sep 6, 2020Updated 5 years ago
- ☆23Oct 7, 2021Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆96Feb 27, 2026Updated 2 months ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Top level for the November shuttle☆12Nov 20, 2021Updated 4 years ago
- ☆22Jul 20, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- UNSUPPORTED INTERNAL toolchain builds☆48Feb 24, 2026Updated 2 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆42Jun 19, 2024Updated last year
- BOOM's Simulation Accelerator.☆13Dec 16, 2021Updated 4 years ago
- ☆72Feb 16, 2023Updated 3 years ago
- A simple implementation of convolutional networks in Matlab☆10Mar 3, 2015Updated 11 years ago
- RTL implementation of Flex-DPE.☆116Feb 22, 2020Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆34Dec 10, 2021Updated 4 years ago
- Using Feature Decomposition method to accelerate GNN inference☆13Sep 27, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository contains software for BeagleWire. Docs of BeagleWire: https://beaglewire.github.io/☆12Aug 17, 2021Updated 4 years ago
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- ☆67May 14, 2022Updated 3 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆20Apr 16, 2026Updated 2 weeks ago
- It is a fpga implementation of an i2c master, framebuffer for sdd1306 display☆11May 14, 2021Updated 4 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆65Oct 9, 2024Updated last year
- Utility for accessing standard Linux spidev devices from userspace.☆11Jan 18, 2017Updated 9 years ago