natu4u / GSOC_TensorCoreLinks
TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
☆22Updated 4 years ago
Alternatives and similar repositories for GSOC_TensorCore
Users that are interested in GSOC_TensorCore are comparing it to the libraries listed below
Sorting:
- ☆33Updated 4 months ago
- course design☆22Updated 7 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆72Updated 2 weeks ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- ☆37Updated 5 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 6 months ago
- ☆36Updated 4 years ago
- A Toy-Purpose TPU Simulator☆19Updated last year
- ☆47Updated 4 months ago
- Algorithmic C Machine Learning Library☆26Updated 8 months ago
- ☆18Updated 3 weeks ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆28Updated this week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆39Updated 7 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- ☆72Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Learn NVDLA by SOMNIA☆42Updated 5 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- Tutorials on HLS Design☆52Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆69Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago