natu4u / GSOC_TensorCoreLinks
TensorCore Vector Processor for Deep Learning - Google Summer of Code Project
☆24Updated 4 years ago
Alternatives and similar repositories for GSOC_TensorCore
Users that are interested in GSOC_TensorCore are comparing it to the libraries listed below
Sorting:
- ☆40Updated 8 months ago
- ☆37Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- ☆88Updated last week
- Algorithmic C Machine Learning Library☆26Updated 3 weeks ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆59Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 9 months ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- ☆28Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆113Updated 2 years ago
- ☆72Updated 2 years ago
- course design☆23Updated 7 years ago
- A DSL for Systolic Arrays☆82Updated 6 years ago
- ☆38Updated 8 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago
- ☆58Updated 7 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆30Updated 3 weeks ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆17Updated 4 years ago
- A Toy-Purpose TPU Simulator☆20Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- A floating-point matrix multiplication implemented in hardware☆31Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆60Updated 5 months ago
- ☆17Updated last month
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated last year
- ☆64Updated 7 months ago
- CNN accelerator☆27Updated 8 years ago