Development area for another repo: Learn_Bluespec_and_RISCV_Design
☆13Jun 28, 2026Updated 2 months ago
Alternatives and similar repositories for DEVEL_Learn_Bluespec_and_RISCV_Design
Users that are interested in DEVEL_Learn_Bluespec_and_RISCV_Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Vim plugin for Bluespec SystemVerilog (BSV)☆12Nov 8, 2020Updated 5 years ago
- ☆11Nov 17, 2025Updated 10 months ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆108Jul 3, 2026Updated 2 months ago
- Learn the Design of a 6-stage pipelined RISC-V CPU☆16Oct 22, 2025Updated 11 months ago
- Consistency checker for memory subsystem traces☆23Oct 10, 2016Updated 9 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A standalone parser for BSV (Bluespec SystemVerilog) written in Go☆14Dec 20, 2016Updated 9 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated 2 years ago
- Source code and speech samples for the DSU-AVO paper accepted to INTERSPEECH 2023☆12May 13, 2024Updated 2 years ago
- ☆23Nov 12, 2020Updated 5 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Jan 7, 2022Updated 4 years ago
- An open-source custom cache generator.☆38Mar 14, 2024Updated 2 years ago
- Documentation for the 2025 IEEE SSCS Chipathon Track on MOSbius☆19Sep 6, 2025Updated last year
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 10 months ago
- Multi-Platform Architecture for Sequence Aligner (MASA) is a flexible software framework that simplifies the creation of DNA sequence ali…☆12Oct 22, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Collection of Spectre-type, Meltdown-type and MDS-type PoCs☆10Aug 25, 2020Updated 6 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- ☆18Jun 22, 2026Updated 3 months ago
- NASTI slave compliant DDRx memory controller.☆11Aug 5, 2016Updated 10 years ago
- ☆14May 15, 2023Updated 3 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- C Compiler written in Kotlin☆13Apr 19, 2024Updated 2 years ago
- my solution for leetcode☆13May 3, 2016Updated 10 years ago
- RISC-V BSV Specification☆24Apr 28, 2026Updated 5 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆36Dec 10, 2021Updated 4 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆15Jan 15, 2024Updated 2 years ago
- A C11 compiler for the discrete logic computer☆21Apr 3, 2024Updated 2 years ago
- Hardware-based VMAF☆11Aug 29, 2025Updated last year
- Fork of main gem5 repo: https://gem5.googlesource.com/public/gem5/☆26Jul 14, 2026Updated 2 months ago
- ☆17Jan 22, 2023Updated 3 years ago
- Fault Injection Automatic Test Equipment☆17Nov 22, 2021Updated 4 years ago
- Connectal is a framework for software-driven hardware development.☆180Oct 16, 2023Updated 2 years ago
- An open-source Simulation Trace Format specification☆17Jun 4, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A survey on architectural simulators focused on CPU caches.☆16Feb 8, 2020Updated 6 years ago
- ☆16Jan 25, 2026Updated 8 months ago
- Machine translation with tinygrad☆19Apr 7, 2024Updated 2 years ago
- A SystemVerilog-based simulation and design of a Last Level Cache (LLC) implementing the MESI protocol, featuring Pseudo-LRU replacement,…☆17Mar 8, 2026Updated 6 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆15Aug 26, 2024Updated 2 years ago
- ☆18Oct 5, 2024Updated last year
- Tool for inferring cache replacement policies with automata learning. Uses LearnLib and Sketch.☆16Apr 21, 2020Updated 6 years ago