Educational materials for RISC-V
☆228Mar 26, 2021Updated 5 years ago
Alternatives and similar repositories for educational-materials
Users that are interested in educational-materials are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆31Feb 10, 2020Updated 6 years ago
- The RISC-V software tools list, as seen on riscv.org☆485Mar 26, 2021Updated 5 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆257Sep 24, 2026Updated last month
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆14Oct 19, 2026Updated last week
- FPGA examples for 8bitworkshop.com☆30May 23, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- The binaries for SaxonSoc Linux and other configurations☆18Mar 23, 2023Updated 3 years ago
- RISC-V Cores, SoC platforms and SoCs☆930Mar 26, 2021Updated 5 years ago
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 9 months ago
- PQR5ASM is a RISC-V Assembler compliant with RV32IM☆19Aug 6, 2026Updated 2 months ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,178Updated this week
- 😎 A curated list of awesome RISC-V implementations☆150Mar 12, 2023Updated 3 years ago
- ☆26Feb 15, 2025Updated last year
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆343Jan 23, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Spike, a RISC-V ISA Simulator☆3,267Updated this week
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 7 years ago
- educational microarchitectures for risc-v isa☆758Sep 1, 2025Updated last year
- Z-Core - A Lightweight RISC-V Processor (RV32IMZicsr)☆15Oct 22, 2026Updated last week
- ☆25Jan 16, 2019Updated 7 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆647Sep 14, 2026Updated last month
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆1,013Nov 15, 2024Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆48Apr 4, 2022Updated 4 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆343Dec 11, 2024Updated last year
- Quickly update a bitstream with new RAM contents☆17Jun 8, 2021Updated 5 years ago
- The official RISC-V getting started guide☆202Feb 12, 2024Updated 2 years ago
- Implementation of a cache memory in verilog☆14Dec 5, 2017Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Jan 6, 2022Updated 4 years ago
- Icestudio Collection to drive displays from Open Source FPGAs☆20Jun 28, 2024Updated 2 years ago
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆478Sep 13, 2024Updated 2 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,196Dec 22, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RISC-V Formal Verification Framework☆633Apr 6, 2022Updated 4 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 7 years ago
- Test Chip General Purpose OpAmp using Skywater SKY130 PDK☆21Mar 1, 2021Updated 5 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆18Apr 4, 2024Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆32Jun 22, 2024Updated 2 years ago
- Opensource building blocks for TinyFPGA microcontrollers and retro computers.☆18Sep 29, 2017Updated 9 years ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,739Updated this week