Educational materials for RISC-V
☆227Mar 26, 2021Updated 4 years ago
Alternatives and similar repositories for educational-materials
Users that are interested in educational-materials are comparing it to the libraries listed below
Sorting:
- The RISC-V software tools list, as seen on riscv.org☆477Mar 26, 2021Updated 4 years ago
- ☆25Jan 16, 2019Updated 7 years ago
- The binaries for SaxonSoc Linux and other configurations☆17Mar 23, 2023Updated 2 years ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆336Dec 11, 2024Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- RISC-V Cores, SoC platforms and SoCs☆915Mar 26, 2021Updated 4 years ago
- Spike, a RISC-V ISA Simulator☆3,028Feb 26, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,837Updated this week
- Quickly update a bitstream with new RAM contents☆16Jun 8, 2021Updated 4 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Apr 18, 2025Updated 10 months ago
- ☆27Feb 15, 2025Updated last year
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆964Nov 15, 2024Updated last year
- Retro computing on the Ulx3s ECP5 FPGA board☆25Mar 3, 2022Updated 4 years ago
- Example LED blinking project for your FPGA dev board of choice☆190Feb 28, 2026Updated last week
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆97Mar 6, 2025Updated last year
- A self-contained online book containing a library of FPGA design modules and related coding/design guides.☆463Sep 13, 2024Updated last year
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,510Feb 25, 2026Updated last week
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆13Feb 28, 2026Updated last week
- RISC-V Tools (ISA Simulator and Tests)☆1,181Dec 22, 2022Updated 3 years ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆571Oct 21, 2025Updated 4 months ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆376Oct 19, 2023Updated 2 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆244Updated this week
- educational microarchitectures for risc-v isa☆741Sep 1, 2025Updated 6 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆333Jan 23, 2022Updated 4 years ago
- Common SystemVerilog components☆718Feb 26, 2026Updated last week
- RISC-V Formal Verification Framework☆624Apr 6, 2022Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago
- Opensource building blocks for TinyFPGA microcontrollers and retro computers.☆17Sep 29, 2017Updated 8 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆649Jan 19, 2026Updated last month
- Simple UVM environment for experimenting with Verilator.☆37Updated this week
- 😎 A curated list of awesome RISC-V implementations☆141Mar 12, 2023Updated 2 years ago
- PicoRV☆43Feb 19, 2020Updated 6 years ago
- The official RISC-V getting started guide☆202Feb 12, 2024Updated 2 years ago
- RISC-V Instruction Set Manual☆4,521Updated this week
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 8 months ago
- ☆46Sep 30, 2025Updated 5 months ago
- Dual MikroBUS board for Upduino 2 FPGA☆18May 24, 2018Updated 7 years ago