包含了SOC设计中的通用IP，如外设、总线结构、基础、验证等
☆148Apr 30, 2026Updated 2 months ago
Alternatives and similar repositories for Opensoc
Users that are interested in Opensoc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 复微杯☆17Aug 7, 2024Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆23Apr 16, 2025Updated last year
- 第八届集创赛紫光同创杯国二FPGA部分☆36Sep 23, 2024Updated last year
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆20Jul 18, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- verilog实现TPU中的脉动阵列计算卷积的module☆174May 10, 2025Updated last year
- riscv指令集，单周期以及五级流水线CPU☆132Jan 6, 2025Updated last year
- A Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.☆568Jul 17, 2025Updated last year
- 中国科学技术大学龙芯杯参赛作品仓库合集☆19Oct 2, 2024Updated last year
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆31Apr 7, 2025Updated last year
- ☆21Feb 10, 2025Updated last year
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆26Jun 30, 2025Updated last year
- ☆40Jul 28, 2025Updated 11 months ago
- FPGA创新设计大赛全国二等奖，Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）☆92Mar 19, 2025Updated last year
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆26Feb 16, 2024Updated 2 years ago
- FPGA based, Real-time processing of audio, including voiceprint recognition, adaptive noise suppression, et al.☆17May 8, 2025Updated last year
- ☆17Jul 30, 2025Updated 11 months ago
- ☆35Jul 9, 2025Updated last year
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated last year
- ☆26Updated this week
- This is a simple Risc-v core for software simulation on FPGA.☆10Apr 9, 2022Updated 4 years ago
- Second Prize in NSCSCC 2024. An out-of-order CPU designed by NoAXI team from HDU. 2024年全国大学生计算机系统能力大赛CPU设计赛（龙芯杯）团队赛二等奖作品☆26Sep 14, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 2023集创赛紫光同创杯一等奖项目☆179Jan 7, 2024Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆148Jul 20, 2023Updated 3 years ago
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆20Apr 7, 2026Updated 3 months ago
- ☆10Dec 15, 2023Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆246Jul 16, 2023Updated 3 years ago
- 基于FPGA的二维卷积识别任务☆26Apr 29, 2023Updated 3 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆248Oct 16, 2025Updated 9 months ago
- A very simple and easy to understand RISC-V core.☆1,503Nov 9, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 一个极其简易的RV32I指令集单核MCU，用户级与特权级支持，仅运行机器模式。☆65Updated this week
- 基于fpga的cordic算法实现☆13Oct 19, 2024Updated last year
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 12 years ago
- Things to learn for new students in the Lab for AI chips and systems of BJTU .☆269Nov 7, 2024Updated last year
- ☆23Jul 14, 2026Updated last week
- PC-side code for PacGoc, enterprise grand prize-winning work at PangoMirco Cup CICC 2024. [第八届集创赛紫光同创杯企业大奖获奖作品]☆20Oct 12, 2024Updated last year
- My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, …☆52Feb 7, 2023Updated 3 years ago