CutestPanda / OpensocLinks
包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等
☆127Updated this week
Alternatives and similar repositories for Opensoc
Users that are interested in Opensoc are comparing it to the libraries listed below
Sorting:
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆221Updated 3 months ago
- CPU Design Based on RISCV ISA☆129Updated last year
- AXI协议规范中文翻译版☆171Updated 3 years ago
- 2023集创赛紫光同创杯一等奖项目☆146Updated 2 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆213Updated 2 years ago
- ☆88Updated last week
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆109Updated 4 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。☆293Updated 7 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆179Updated 2 years ago
- FPGA实现简单的图像处理算法☆70Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆142Updated 2 years ago
- 代码在这个库里 Code is here☆65Updated 2 weeks ago
- verilog实现TPU中的脉动阵列计算卷积的module☆156Updated 9 months ago
- AMBA bus lecture material☆508Updated 6 years ago
- AXI总线连接器☆105Updated 5 years ago
- 数字IC设计 学习笔记☆159Updated 4 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆89Updated 11 months ago
- 2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二 等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition☆15Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Updated 7 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22Updated last year
- IC implementation of Systolic Array for TPU☆330Updated last year
- FPGA project☆237Updated 3 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆267Updated last year
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆46Updated last year
- ☆153Updated 2 months ago
- The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…☆58Updated last year
- fpga跑sobel识别算法☆44Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Updated last year