Alternatives and similar repositories for arty-cm0-designstart

Users that are interested in arty-cm0-designstart are comparing it to the libraries listed below

• dineshannayya / usb1_host
  USB1.1 Host Controller + PHY
  ☆14Updated 3 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆33Updated 5 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆19Updated 2 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆18Updated this week
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆15Updated 10 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• freecores / usb_phy
  USB 1.1 PHY
  ☆11Updated 10 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 10 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆24Updated 4 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆38Updated 3 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆22Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆44Updated 5 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆67Updated 7 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• freecores / uart2spi
  UART To SPI
  ☆17Updated 10 years ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 10 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 9 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• rbarzic / ml-ahb-gen
  A Verilog AMBA AHB Multilayer interconnect generator
  ☆12Updated 7 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• freecores / wdsp
  DSP WishBone Compatible Cores
  ☆13Updated 10 years ago