☆18Jul 23, 2018Updated 8 years ago
Alternatives and similar repositories for JPEG_Encoder
Users that are interested in JPEG_Encoder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module☆21Feb 8, 2018Updated 8 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆18Aug 31, 2020Updated 6 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Jul 25, 2018Updated 8 years ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆33May 15, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implements the DBSCAN Clustering algorithm☆48Mar 23, 2020Updated 6 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆40Oct 25, 2020Updated 5 years ago
- A configurable USB 2.0 device core☆31Jun 12, 2020Updated 6 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 6 years ago
- UPDuino v1.0 - PCB Design Files, Designs, Documentation☆21Jul 17, 2018Updated 8 years ago
- ☆31Jan 23, 2021Updated 5 years ago
- MIPI testing with LiteX on CrossLink-NX☆14Jan 29, 2026Updated 7 months ago
- FPGA图像处理仿真平台☆31Apr 25, 2022Updated 4 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Dec 15, 2017Updated 8 years ago
- Applying various image enhancement algorithms on Night Vision IR images using Xilinx Vivado☆16Oct 27, 2023Updated 2 years ago
- 一款Cyclone Ⅳ(EP4CE6E22C8N)的FPGA板,板载JTAG下载电路、HDMI(output)、UART、SDRAM、TFT-LCD等☆18Jun 29, 2023Updated 3 years ago
- Streaming video over USB using FT232H and Cyclone IV FPGA.☆15Feb 26, 2023Updated 3 years ago
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆15Aug 7, 2022Updated 4 years ago
- JPEG Compression using DCT (Discrete Cosine Transform) and DWT (Discrete Wavelet Transform) in Matlab.☆10Nov 26, 2019Updated 6 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 9 years ago
- A Video display simulator☆185May 16, 2025Updated last year
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆28Aug 27, 2026Updated last week
- some news or blogs for new computer architecture like risc-v, xPU, ASIC, etc....☆15Jan 6, 2020Updated 6 years ago
- Yet another alternative curriculum vitae/résumé class with LaTeX☆13May 7, 2020Updated 6 years ago
- maskcnn_benchmark based on mobilenetv2☆12Nov 11, 2019Updated 6 years ago
- JPEG的正向离散余弦变化、量化、Z字形编码、对DC编码、AC编码、熵编码以及图像重构☆13May 27, 2019Updated 7 years ago
- MTCNN with convolution reprogramed in c☆14Jul 25, 2019Updated 7 years ago
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Getting started project for the DigiKey M2S010-MKR-KIT☆16Sep 6, 2018Updated 8 years ago
- Lab assignment on indoor localization for CAN405☆14Nov 29, 2022Updated 3 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 4 years ago
- ☆19Mar 6, 2020Updated 6 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- PNG encoder, implemented in VHDL☆23Mar 30, 2024Updated 2 years ago
- Open Source 4k CSI-2 Rx core for Xilinx FPGAs☆420Nov 14, 2018Updated 7 years ago