UviDTE-FPSoC / Zynq7000-dnn-inferenceLinks
Deep Neural Network inference using Xilinx Zynq-7000 chip.
☆23Updated 5 years ago
Alternatives and similar repositories for Zynq7000-dnn-inference
Users that are interested in Zynq7000-dnn-inference are comparing it to the libraries listed below
Sorting:
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆23Updated 6 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- Vitis HLS Library for FINN☆202Updated this week
- 中文:☆101Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆70Updated 6 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆236Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆68Updated 4 months ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- FPGA☆158Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆46Updated 5 years ago
- Zynq-7000 DPU TRD☆45Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆159Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- hls code zynq 7020 pynq z2 CNN☆83Updated 6 years ago
- Low-Precision YOLO on PYNQ with FINN☆33Updated last year
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆113Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 6 months ago
- ☆272Updated last year
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- ☆53Updated 2 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆222Updated 3 months ago
- DPU on PYNQ☆224Updated last year
- FPGA and GPU acceleration of LeNet5☆34Updated 6 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆150Updated 4 years ago