buttercutter / riffa2
Full duplex version of https://github.com/KastnerRG/riffa/issues/30
☆26Updated 6 years ago
Alternatives and similar repositories for riffa2:
Users that are interested in riffa2 are comparing it to the libraries listed below
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆53Updated 3 years ago
- Ethernet switch implementation written in Verilog☆47Updated last year
- understanding of cocotb (In Chinese Only)☆16Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆62Updated 6 months ago
- Gigabit Ethernet UDP communication driver☆75Updated 5 years ago
- Must-have verilog systemverilog modules☆33Updated 3 years ago
- Demonstration of the AXI DMA engine on the ZedBoard☆53Updated 4 years ago
- Hardware Assisted IEEE 1588 IP Core☆28Updated 10 years ago
- ☆59Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Verilog Ethernet Switch (layer 2)☆43Updated last year
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆92Updated 9 months ago
- Ethernet MAC 10/100 Mbps☆81Updated 5 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- ☆25Updated 3 years ago
- This repo contains the Limago code☆84Updated this week
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- ☆23Updated 4 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆70Updated last year
- ☆30Updated 5 years ago
- 10G Low Latency Ethernet☆53Updated last year
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆100Updated 6 years ago