cxdzyq1110 / posture_recognition_CNNLinks
To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture rec…
☆53Updated 7 years ago
Alternatives and similar repositories for posture_recognition_CNN
Users that are interested in posture_recognition_CNN are comparing it to the libraries listed below
Sorting:
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆96Updated last year
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- AHB DMA 32 / 64 bits☆56Updated 10 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆45Updated 5 years ago
- 文档编写☆13Updated 4 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆72Updated 6 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- ☆36Updated 9 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆59Updated 4 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- ☆65Updated 6 years ago
- AXI Interconnect☆50Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 10 months ago
- ☆25Updated 4 years ago
- AIChip 2021 project, NCKU☆18Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆10Updated 5 years ago