cxdzyq1110 / posture_recognition_CNNLinks
To help machines learn what we human beings are doing via a camera is important. Once it comes true, machines can make different responses to all kinds of human's postures. But the process is very difficult as well, because usually it is very slow and power-consuming, and requires a very large memory space. Here we focus on real-time posture rec…
☆55Updated 7 years ago
Alternatives and similar repositories for posture_recognition_CNN
Users that are interested in posture_recognition_CNN are comparing it to the libraries listed below
Sorting:
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆191Updated last year
- This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.☆24Updated 6 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆50Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆104Updated 2 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- CNN accelerator implemented with Spinal HDL☆156Updated last year
- 文档编写☆13Updated 5 years ago
- 使用FPGA实现CNN模型☆15Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- 3×3脉动阵列乘法器☆50Updated 6 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆62Updated 7 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- hls code zynq 7020 pynq z2 CNN☆89Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- FPGA/AES/LeNet/VGG16☆109Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- ☆45Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- AXI总线连接器☆105Updated 5 years ago
- fpga跑sobel识别算法☆45Updated 4 years ago
- IC Verification & SV Demo☆54Updated 4 years ago
- ☆38Updated 10 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.