This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length is of length 249 symbols and it can detect and correct upto 3 error symbols.
☆24Dec 17, 2019Updated 6 years ago
Alternatives and similar repositories for Reed-Solomon-
Users that are interested in Reed-Solomon- are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Reed-Solomon (RS) Encoder/Decoder + Channel Simulation☆19Mar 24, 2022Updated 4 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 5 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- Undergraduate digital circuit laboratory☆29Jan 4, 2024Updated 2 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆19Jul 22, 2021Updated 4 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆22Jul 7, 2024Updated last year
- ☆78Feb 4, 2021Updated 5 years ago
- ☆31Apr 1, 2017Updated 9 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 4 months ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆13Dec 16, 2020Updated 5 years ago
- ☆15Jun 28, 2021Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆79Jan 2, 2021Updated 5 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆16Aug 26, 2021Updated 4 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- tool for converting vcd(value change dump) to ate pattern.☆11Oct 22, 2015Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A collection of examples showcasing PyCDE and Mini RISC-V implementation.☆10Apr 6, 2026Updated last week
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆30Dec 17, 2020Updated 5 years ago
- asynchronous fifo based on verilog☆15Apr 14, 2022Updated 4 years ago
- (NO LONGER MAINTAINED) Clone of RTAI from https://www.rtai.org☆28Jan 11, 2016Updated 10 years ago
- LimeSDR with Matlab☆11Dec 30, 2019Updated 6 years ago
- C++ 17 Hardware abstraction layer generator from systemrdl☆15Apr 12, 2026Updated last week
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- this repository is vim cfg for verilog.☆55Feb 9, 2026Updated 2 months ago
- AXI4-Stream FIR filter IP☆19Nov 4, 2022Updated 3 years ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆19May 26, 2021Updated 4 years ago
- Source files for Getting to Know Vivado course☆18Sep 2, 2020Updated 5 years ago
- Polar Codes Implementation on Vhdl☆14Jun 4, 2016Updated 9 years ago
- ☆15Mar 28, 2026Updated 3 weeks ago
- Real-Time Image Processing for ASIC/FGPA☆24Feb 23, 2022Updated 4 years ago