TCP/IP and UDP/IP protocol stack off-loading
☆19Aug 9, 2020Updated 6 years ago
Alternatives and similar repositories for HardORB
Users that are interested in HardORB are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Gigabit MAC + UDP/TCP/IP offload Engine☆35Sep 17, 2019Updated 7 years ago
- Digital System Design and Generation - System Verilog Projects☆10Apr 27, 2016Updated 10 years ago
- Katze Ethernet Pmod Compatible Module☆12Jul 26, 2026Updated 3 months ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆36May 20, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SDRAM controller with AXI4 interface☆110Aug 8, 2019Updated 7 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- ISP☆14Nov 25, 2023Updated 2 years ago
- Complete UCIe v2.0 Controller RTL Implementation with Revolutionary 128 Gbps PAM4 Signaling - Architecture Design Complete, Ready for RTL…☆41Aug 30, 2025Updated last year
- Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.☆13Nov 24, 2017Updated 8 years ago
- ☆10Nov 13, 2023Updated 2 years ago
- The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"☆11Oct 7, 2023Updated 3 years ago
- EECS 470 Final Project☆11Apr 22, 2013Updated 13 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- 📸 ADCs for faster image sensors☆13Updated this week
- Basic implementation of a MOLDUDP64 server☆13Jan 6, 2016Updated 10 years ago
- Open Source Silicon Development Testing Unit using JTAG☆15Apr 25, 2026Updated 6 months ago
- This project intends to develop tools around AFDX. (Avionics Full Duplex Switched Ethernet).☆10Oct 27, 2010Updated 16 years ago
- This repo contains the Limago code☆99May 8, 2025Updated last year
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- IHP SG13CMOS5L PDK☆19Sep 23, 2026Updated last month
- ☆14Nov 5, 2017Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆15Sep 9, 2022Updated 4 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 12 years ago
- AFDX protocol dissector for wireshark☆16Jun 17, 2019Updated 7 years ago
- Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism☆62Feb 27, 2022Updated 4 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆124Nov 27, 2017Updated 8 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 6 years ago
- TCP Offload Engine☆79Nov 18, 2017Updated 8 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆16Feb 18, 2025Updated last year
- ☆20Dec 21, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AmorphOS open source FPGA operating system project☆10Apr 16, 2020Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).☆12Oct 14, 2017Updated 9 years ago
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆81Mar 6, 2019Updated 7 years ago
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- Open-NVM Software Source Code☆10Jul 3, 2015Updated 11 years ago
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year