antmicro / lpddr4-test-board
Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM
☆36Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for lpddr4-test-board
- Open-source high performance AXI4-based HyperRAM memory controller☆57Updated 2 years ago
- USB Full Speed PHY☆39Updated 4 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆47Updated 4 years ago
- USB 2.0 Device IP Core☆52Updated 7 years ago
- Extensible FPGA control platform☆53Updated last year
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆61Updated 5 months ago
- SPI-Flash XIP Interface (Verilog)☆35Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆59Updated 3 years ago
- ☆46Updated 2 years ago
- Basic USB-CDC device core (Verilog)☆73Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- Experimental Xilinx Artix-7 driven Data Center Security Communication Module☆48Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆37Updated 3 years ago
- turbo 8051☆28Updated 7 years ago
- Xilinx virtual cable server for generic FTDI 4232H.☆50Updated 9 months ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆87Updated 4 years ago
- DisplayPort IP-core☆50Updated 2 weeks ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆27Updated 3 years ago
- Wishbone interconnect utilities☆36Updated 5 months ago
- USB serial device (CDC-ACM)☆36Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆55Updated 2 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 5 years ago
- Bitstream relocation and manipulation tool.☆39Updated last year
- IEEE P1735 decryptor for VHDL☆25Updated 9 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆38Updated last year
- ☆80Updated 7 years ago
- Small footprint and configurable JESD204B core☆40Updated last month
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- UART -> AXI Bridge☆55Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆75Updated 2 years ago