xk264：AVC/H.264 Video Encoder IP Core (RTL)
☆53Mar 22, 2023Updated 2 years ago
Alternatives and similar repositories for xk264
Users that are interested in xk264 are comparing it to the libraries listed below
Sorting:
- xk265：HEVC/H.265 Video Encoder IP Core (RTL)☆269Apr 9, 2023Updated 2 years ago
- xkDLA：XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Dec 8, 2017Updated 8 years ago
- Convert H264 stream to flv stream☆11Feb 9, 2015Updated 11 years ago
- A stream to RTL compiler based on MLIR and CIRCT☆16Nov 15, 2022Updated 3 years ago
- xkISP：Xinkai ISP IP Core (HLS)☆302Mar 14, 2023Updated 2 years ago
- eeprog is a Linux C program that allows you to read and write to 24Cxx EEPROMs.☆14Apr 26, 2023Updated 2 years ago
- P4 compatible HLS modules☆11Apr 23, 2018Updated 7 years ago
- 利用ZYNQ7020实现SAR数据采集系统，其中包含硬件设计代码、上位机、测试程序。☆14Feb 27, 2025Updated last year
- mpp decode h264,rga resize, drm display by hdmi☆15Aug 20, 2020Updated 5 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 3 years ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- Open Source SSD Controller. NVMe and Lightstor variants☆18May 21, 2014Updated 11 years ago
- ☆15Dec 9, 2018Updated 7 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 9 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs b…☆319May 16, 2021Updated 4 years ago
- zynqmp_cam_isp_demo linux软件项目☆22Dec 18, 2022Updated 3 years ago
- prebuild package for cross compiling riscv☆17Dec 28, 2021Updated 4 years ago
- ☆29Feb 20, 2024Updated 2 years ago
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆26Apr 24, 2019Updated 6 years ago
- Vivado诸多IP，包括图像处理等☆234Jul 28, 2024Updated last year
- development interface mil-std-1553b for system on chip☆24Feb 2, 2018Updated 8 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Jun 18, 2020Updated 5 years ago
- HW accelerated h264 encoding on the Allwinner V3s w/ mainline Linux☆24Jul 27, 2023Updated 2 years ago
- An FPGA-based NetTLP adapter☆27Mar 10, 2020Updated 5 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆32Mar 13, 2025Updated 11 months ago
- ☆44Updated this week
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- ☆24Feb 21, 2019Updated 7 years ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆35Nov 26, 2018Updated 7 years ago
- Verilog Repository for GIT☆35May 4, 2021Updated 4 years ago
- Tensorflow workspaces for training your custom models of K210☆67Nov 25, 2019Updated 6 years ago