hlslibs / ac_mathLinks
Algorithmic C Math Library
☆67Updated last week
Alternatives and similar repositories for ac_math
Users that are interested in ac_math are comparing it to the libraries listed below
Sorting:
- Algorithmic C Datatypes☆134Updated last week
- Tutorials on HLS Design☆52Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last week
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆54Updated 7 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Algorithmic C Digital Signal Processing (DSP) Library☆53Updated last week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 11 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated last week
- Open Source PHY v2☆33Updated last year
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆127Updated last week
- ☆35Updated 2 years ago
- FOS - FPGA Operating System☆73Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- PACoGen: Posit Arithmetic Core Generator☆76Updated 6 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆116Updated 2 years ago
- Open-Source HLS Examples for Microchip FPGAs☆49Updated this week
- Example code for Modern SystemC using Modern C++☆69Updated 3 years ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- PCI Express controller model☆71Updated 3 years ago
- Next generation CGRA generator☆118Updated last week
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Caffe to VHDL☆68Updated 5 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Learn systemC with examples☆127Updated 3 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 7 years ago