silicontalks01 / OpenDLA
A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.
☆15Updated 7 years ago
Alternatives and similar repositories for OpenDLA:
Users that are interested in OpenDLA are comparing it to the libraries listed below
- A discussion group on Open Source Deep Learning Accelerator, with technical reports and potential hardware/software issues.☆141Updated 7 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆47Updated 8 years ago
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- ☆67Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆22Updated 8 years ago
- ☆85Updated 2 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- ☆25Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆100Updated 6 years ago
- Public release☆50Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- ☆83Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Updated 5 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
- Support for Rocket Chip on Zynq FPGAs☆40Updated 5 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆54Updated 4 months ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- round robin arbiter☆71Updated 10 years ago
- ☆53Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆20Updated 5 years ago