Alternatives and similar repositories for Violet

Users that are interested in Violet are comparing it to the libraries listed below

• skyzh / mips-simulator
  💻 A 5-stage pipeline MIPS CPU design in Haskell.
  ☆35Updated 5 years ago
• imkiva / valheim
  Just for fun riscv64 emulator, which boots the Linux.
  ☆41Updated 3 years ago
• rustcc / GEFS
  Game Engine From Scratch -- Rust China Conference 2020 topic by LemonHX and his team.
  ☆14Updated 5 years ago
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 4 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 3 months ago
• nbdd0121 / r2vm
  Rust RISC-V Virtual Machine
  ☆111Updated 4 months ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆27Updated 5 years ago
• memoryleak47 / slotted-egraphs
  ☆37Updated 3 months ago
• xen0n / larva
  PoC LoongArch - RISC-V emulator
  ☆32Updated 2 years ago
• rcore-os / aCore
  Asynchronous OS kernel written in Rust.
  ☆32Updated 5 years ago
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• bollu / lz
  A minimal in MLIR dialect along the lines of STG to represent laziness.
  ☆16Updated 3 years ago
• Harry-Chen / rust-mips
  Rust library for low-level abstraction of MIPS processors
  ☆31Updated 5 years ago
• djg / verilated-rs
  Verilator Porcelain
  ☆49Updated 2 years ago
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆90Updated 3 weeks ago
• trackoor / AwesomePL
  A Collection of Papers & Notes in Programming Language & Formal Verification
  ☆17Updated 3 years ago
• PrincetonUniversity / DeepSpecDB
  ☆27Updated last month
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆13Updated 5 years ago
• SkiFire13 / typst-prooftree
  Prooftrees for Typst - Inspired by Latex's bussproofs
  ☆20Updated last year
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆172Updated 2 years ago
• djanderson / riscv-5stage-simulator
  A 5-stage pipelining RISC-V 32I simulator written in Rust.
  ☆19Updated 4 years ago
• fintelia / riscv-decode
  Simple library for decoding RISC-V instructions
  ☆24Updated last month
• elliottt / easy-smt
  Easy SMT solver interaction
  ☆34Updated 4 months ago
• allvm / allvm-tools
  ALLVM Tools
  ☆56Updated 3 years ago
• pku-minic / first-step-rs
  Take your first step in writing a compiler. Implemented in Rust.
  ☆16Updated 2 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 5 months ago
• rcore-os / trapframe-rs
  Handle TrapFrame across kernel and user space on multiple ISAs.
  ☆35Updated last year
• egraphs-good / extraction-gym
  benchmarking e-graph extraction
  ☆48Updated 7 months ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆32Updated 3 years ago
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆56Updated 7 years ago