hichem / I2C
SystemC Design of a Master/Slave I2C Bus
☆18Updated 9 years ago
Alternatives and similar repositories for I2C
Users that are interested in I2C are comparing it to the libraries listed below
Sorting:
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆17Updated 11 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- RISC-V processor model☆10Updated 4 years ago
- gdb python scripts for SystemC design introspection and tracing☆33Updated 6 years ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- SoCRocket - Core Repository☆35Updated 8 years ago
- SoC based on RISC V ISA☆10Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- ☆22Updated 8 years ago
- A CSV file parser, written in SystemVerilog☆25Updated 8 years ago
- This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.☆17Updated last week
- use pivpi to drive testbench event☆21Updated 8 years ago
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆24Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆37Updated 5 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆104Updated 2 weeks ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Framework Open EDA Gui☆65Updated 5 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆35Updated 5 months ago
- Main repo for Go2UVM source code, examples and apps☆20Updated 2 years ago
- Advanced Debug Interface☆15Updated 3 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆59Updated 3 weeks ago