Alternatives and similar repositories for I2C

Users that are interested in I2C are comparing it to the libraries listed below

• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆27Updated 2 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 12 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆33Updated 6 years ago
• edaa-org / IPXACT-Schema
  This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.
  ☆19Updated 4 months ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆72Updated 6 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆31Updated 9 months ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆12Updated 9 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated 9 months ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆116Updated this week
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 7 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 9 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 7 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated last month
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• GordonMcGregor / vcd_parser
  A VCD parser object
  ☆39Updated 12 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆15Updated 4 years ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 9 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated last week
• systemc / systemc-2.3
  New release of the systemc libraries
  ☆123Updated 13 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 3 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆47Updated 10 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last week