Alternatives and similar repositories for I2C

Users that are interested in I2C are comparing it to the libraries listed below

• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated 9 months ago
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆26Updated 2 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 11 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• edaa-org / IPXACT-Schema
  This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.
  ☆19Updated 3 months ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆31Updated 9 months ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆53Updated last year
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆113Updated this week
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆30Updated 9 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• ripopov / gdb_systemc_trace
  gdb python scripts for SystemC design introspection and tracing
  ☆33Updated 6 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 9 years ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 3 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 9 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆12Updated 9 years ago
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated 3 months ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆28Updated 9 months ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• agra-uni-bremen / riscv-freertos
  FreeRTOS port for the RISC-V Virtual Prototype
  ☆14Updated 4 years ago
• systemc / systemc-2.3
  New release of the systemc libraries
  ☆123Updated 13 years ago