Alternatives and similar repositories for I2C

Users that are interested in I2C are comparing it to the libraries listed below

• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆26Updated 3 years ago
• edaa-org / IPXACT-Schema
  This repository provides the IEEE 1685 IP-XACT schema files for a Git submodule integration.
  ☆20Updated 8 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated last year
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆27Updated 9 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 13 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Updated 5 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 3 months ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆14Updated last year
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆34Updated 2 months ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 12 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆42Updated 13 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated 2 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 9 years ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆22Updated 8 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆32Updated 10 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆19Updated 4 months ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆45Updated 10 years ago
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 7 months ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆16Updated 6 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 7 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆65Updated 2 weeks ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆12Updated 6 years ago
• kactus2 / ipxactexamplelib
  Contains examples to start with Kactus2.
  ☆23Updated last year