Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
☆14May 11, 2014Updated 12 years ago
Alternatives and similar repositories for coursera-vlsicad
Users that are interested in coursera-vlsicad are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆22Nov 26, 2018Updated 7 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆14Mar 5, 2017Updated 9 years ago
- Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”☆12Jan 7, 2026Updated 10 months ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- ☆16Jun 28, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Code for new techniques of VLSI placement☆13Oct 11, 2013Updated 13 years ago
- Project Name: Automated Circuit To MAGIC VLSI layout Using Open Source EDA Tools☆13Dec 24, 2020Updated 5 years ago
- Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations☆14Jan 22, 2020Updated 6 years ago
- Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placement☆15Nov 14, 2024Updated last year
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆18Mar 22, 2017Updated 9 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 5 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- This repository contains my coding implementations for Udemy based Embedded Systems and RTOS courses.☆14Sep 16, 2021Updated 5 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- VLSI Design of an 8 x 2 SRAM Array | Cadence Virtuoso☆12Feb 10, 2020Updated 6 years ago
- This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projec…☆13Jul 12, 2025Updated last year
- Repository for the course "Sensor Fusion and Non-Linear Filtering" - SSY345 at Chalmers University of Technology☆14May 19, 2019Updated 7 years ago
- Digital IC design and vlsi notes☆15Jun 24, 2020Updated 6 years ago
- Implementation of the ePlace algorithm on the AMD Versal architecture, utilizing AIE, PL, and PS regions of the chip.☆11Oct 30, 2026Updated last week
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆62Nov 4, 2024Updated 2 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆51Mar 22, 2019Updated 7 years ago
- Using Xilinx Vitis, Vivado and Vitis HLS design program and running on Xilinx ZCU104 board☆13Sep 22, 2022Updated 4 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆26May 2, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- CORDIC VLSI-IP for deep learning activation functions☆15Jul 13, 2019Updated 7 years ago
- ☆14Oct 23, 2018Updated 8 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- Advanced Machine Learning and Signal Processing IBM☆17Sep 6, 2019Updated 7 years ago
- Analog and mixed-signal automatic placer☆14Feb 14, 2023Updated 3 years ago
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆45Aug 25, 2026Updated 2 months ago
- coursera code☆13Jun 27, 2013Updated 13 years ago
- ☆10Aug 21, 2026Updated 2 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆19Dec 16, 2017Updated 8 years ago
- RTL to GDS via Cadence Tools☆20May 17, 2022Updated 4 years ago
- ☆23May 26, 2026Updated 5 months ago
- Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs☆12Jan 12, 2023Updated 3 years ago
- RTL design of Systolic Arrays for matrix multiplication.☆16Dec 17, 2023Updated 2 years ago
- Introductory course for Perl 5 through examples, geared towards VLSI engineers☆54Oct 1, 2020Updated 6 years ago
- ☆27Feb 27, 2021Updated 5 years ago
Are these results useful?