Project 2.2 Frequency counter
☆12May 30, 2025Updated last year
Alternatives and similar repositories for frequency_counter
Users that are interested in frequency_counter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Verilog Project☆24Aug 30, 2021Updated 5 years ago
- ☆24Oct 5, 2026Updated last week
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆23Apr 15, 2021Updated 5 years ago
- FPGA CryptoNight V7 Minner☆32Aug 26, 2019Updated 7 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- Makes context oriented functions easily usable via `|>` pipeline operator.☆16Aug 2, 2018Updated 8 years ago
- Probabilistic inference for models of behaviour☆13Mar 5, 2026Updated 7 months ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- EE 287 2012 Fall☆34Mar 11, 2013Updated 13 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Sep 24, 2026Updated 2 weeks ago
- A small and simple rv32i core written in Verilog☆19Jul 29, 2022Updated 4 years ago
- Convert Verilog to a Hardcaml design☆23Jul 10, 2026Updated 3 months ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆12Oct 2, 2026Updated last week
- Controller module for RISC-V core CI/CD☆18Sep 17, 2026Updated 3 weeks ago
- Python-like syntax for Rust-like performance☆16Mar 17, 2023Updated 3 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The Faust Online Documentation☆12Updated this week
- A C++ wrapper for the Apple metal-cpp library to make it easier to run compute kernels on the GPU☆11Jun 11, 2025Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆62Nov 30, 2022Updated 3 years ago
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Jul 12, 2024Updated 2 years ago
- Clock Fault Injector - Clock Glitching Attack with Chipwhisperer☆10Dec 26, 2024Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- Cadence Audio Framework - Hostless☆13Apr 12, 2022Updated 4 years ago
- Submission template for Tiny Tapeout 7 - Verilog HDL Projects☆22May 30, 2024Updated 2 years ago
- A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.☆10Aug 27, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 📶 Check you internet downlink speed without consuming your data☆11Aug 9, 2019Updated 7 years ago
- Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board☆11Jan 1, 2024Updated 2 years ago
- Show schedules for cinemas across Nigeria.☆10Jan 8, 2019Updated 7 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 12 years ago
- An interactive, collaborative and beautiful board☆14Nov 16, 2024Updated last year
- Polyfills the a[download] attribute☆13Sep 9, 2026Updated last month
- https://pypi.python.org/pypi/Verilog_VCD☆22Mar 16, 2017Updated 9 years ago