Project 2.2 Frequency counter
☆12May 30, 2025Updated 11 months ago
Alternatives and similar repositories for frequency_counter
Users that are interested in frequency_counter are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- FPGA CryptoNight V7 Minner☆31Aug 26, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- EE 287 2012 Fall☆34Mar 11, 2013Updated 13 years ago
- Makes context oriented functions easily usable via `|>` pipeline operator.☆16Aug 2, 2018Updated 7 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- DSP Blocks for the nMigen (Python) Toolbox☆11Nov 5, 2020Updated 5 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- Faust major mode for editing faust code (.dsp files)☆16Oct 4, 2020Updated 5 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14May 11, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆14Jul 23, 2020Updated 5 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11May 16, 2026Updated last week
- Probabilistic inference for models of behaviour☆13Mar 5, 2026Updated 2 months ago
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 5 years ago
- Convert Verilog to a Hardcaml design☆19May 18, 2026Updated last week
- The project is tailored for quick audio start-up with the SHARC Audio Module board. It uses the various reusable component building block…☆16Mar 26, 2026Updated last month
- Python-like syntax for Rust-like performance☆16Mar 17, 2023Updated 3 years ago
- The Faust Online Documentation☆12Mar 20, 2026Updated 2 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- FPGA for uSDR☆22Apr 18, 2026Updated last month
- Implementation of quadcopter flight dynamics & control.☆17Apr 23, 2023Updated 3 years ago
- Demonstration of the YoWASP toolchain being used with Visual Studio Code to program a Radiona ULX3S board☆11Jan 1, 2024Updated 2 years ago
- A C++ wrapper for the Apple metal-cpp library to make it easier to run compute kernels on the GPU☆11Jun 11, 2025Updated 11 months ago
- Cadence Audio Framework - Hostless☆13Apr 12, 2022Updated 4 years ago
- NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖☆18Aug 17, 2024Updated last year
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Jul 12, 2024Updated last year
- This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…☆60Nov 30, 2022Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- My Solution to chapter exercises for Digital Design 6e - With Introduction to The Verilog HDL, VHDL and System Verilog☆18Mar 12, 2020Updated 6 years ago
- AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.☆28Apr 6, 2026Updated last month
- A Verilog parser for Haskell.☆37Jul 6, 2021Updated 4 years ago
- ☆15Nov 30, 2023Updated 2 years ago
- 📶 Check you internet downlink speed without consuming your data☆11Aug 9, 2019Updated 6 years ago
- A simple example of using the SDAccel build flow for AWS EC2's F1 instance type. Trys to avoid magic makefiles.☆10Aug 27, 2017Updated 8 years ago
- Controller module for RISC-V core CI/CD☆17May 23, 2025Updated last year