marshall-999 / UVMReference
This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
☆10Updated 3 years ago
Alternatives and similar repositories for UVMReference:
Users that are interested in UVMReference are comparing it to the libraries listed below
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- ☆23Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆22Updated 2 years ago
- ☆14Updated 2 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆12Updated 2 years ago
- ☆17Updated 9 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- Maven Silicon Project☆17Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆19Updated 5 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- AHB to APB Bridge VIP☆28Updated 5 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆15Updated 6 months ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆16Updated 7 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆20Updated 7 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 6 years ago
- ☆16Updated 2 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago
- Verification IP for APB protocol☆56Updated 4 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆10Updated 5 years ago
- ☆18Updated 2 years ago
- ☆36Updated last year
- ☆12Updated 9 years ago
- An uvm verification env for ahb2apb bridge☆47Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago