marshall-999 / UVMReference
This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
☆13Updated 3 years ago
Alternatives and similar repositories for UVMReference
Users that are interested in UVMReference are comparing it to the libraries listed below
Sorting:
- UVM Testbench for synchronus fifo☆17Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- ☆25Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Verification IP for APB protocol☆63Updated 4 years ago
- Maven Silicon Project☆17Updated 6 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆20Updated 10 months ago
- Verification IP for APB protocol☆26Updated 4 years ago
- ☆17Updated 10 years ago
- ☆15Updated 2 years ago
- ☆19Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- AHB to APB Bridge VIP☆29Updated 6 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- ☆40Updated last year
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- AXI Interconnect☆47Updated 3 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆32Updated 4 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆15Updated last year
- Sample UVM code for axi ram dut☆32Updated 3 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- ☆21Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 3 months ago
- ☆12Updated 9 years ago